Patents by Inventor Takayuki Nakaji

Takayuki Nakaji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10385802
    Abstract: A piston of an internal combustion engine includes a crown surface, a first cavity, and a second cavity. The crown surface forms an internal wall surface of a combustion chamber. The first cavity is a depression provided in the crown surface. The second cavity is a depression provided inside the first cavity. The first cavity includes an upstream portion located upstream of the second cavity in a flow direction of a tumble flow flowing along the crown surface and a downstream portion located downstream of the second cavity in the flow direction. The upstream portion extends further in the flow direction than the downstream portion.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: August 20, 2019
    Assignee: SUBARU CORPORATION
    Inventor: Takayuki Nakaji
  • Patent number: 9972445
    Abstract: Provided are an electrolytic capacitor with high withstand voltage capable of preventing deterioration of withstand voltage characteristics caused by lead-free reflow or the like and improving ESR characteristics, and a manufacturing method thereof. The electrolytic capacitor is obtained by impregnating a capacitor element in which an anode electrode foil and a cathode electrode foil are wound with a separator interposed, with a dispersion containing: particles of a conductive polymer; sorbitol or sorbitol and polyalcohol; and a solvent so as to form a solid electrolyte layer containing 60 to 92 wt % of the sorbitol or the sorbitol and polyalcohol, and by filling an electrolytic solution containing ethylene glycol in a gap portion in the capacitor element on which the solid electrolyte layer is formed.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: May 15, 2018
    Assignee: NIPPON CHEMI-CON CORPORATION
    Inventors: Kazuya Koseki, Kouichi Kuroda, Masao Sakakura, Tomohiro Matsuzaki, Takayuki Nakaji
  • Publication number: 20180080407
    Abstract: A piston of an internal combustion engine includes a crown surface, a first cavity, and a second cavity. The crown surface forms an internal wall surface of a combustion chamber. The first cavity is a depression provided in the crown surface. The second cavity is a depression provided inside the first cavity. The first cavity includes an upstream portion located upstream of the second cavity in a flow direction of a tumble flow flowing along the crown surface and a downstream portion located downstream of the second cavity in the flow direction. The upstream portion extends further in the flow direction than the downstream portion.
    Type: Application
    Filed: June 14, 2017
    Publication date: March 22, 2018
    Applicant: SUBARU CORPORATION
    Inventor: Takayuki NAKAJI
  • Publication number: 20150287540
    Abstract: Provided are an electrolytic capacitor with high withstand voltage capable of preventing deterioration of withstand voltage characteristics caused by lead-free reflow or the like and improving ESR characteristics, and a manufacturing method thereof. The electrolytic capacitor is obtained by impregnating a capacitor element in which an anode electrode foil and a cathode electrode foil are wound with a separator interposed, with a dispersion containing: particles of a conductive polymer; sorbitol or sorbitol and polyalcohol; and a solvent so as to forma solid electrolyte layer containing 60 to 92 wt % of the sorbitol or the sorbitol and polyalcohol, and by filling an electrolytic solution containing ethylene glycol in a gap portion in the capacitor element on which the solid electrolyte layer is formed.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 8, 2015
    Inventors: Kazuya KOSEKI, Kouichi KURODA, Masao SAKAKURA, Tomohiro MATSUZAKI, Takayuki NAKAJI
  • Patent number: 8324706
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
  • Publication number: 20100244137
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Application
    Filed: June 10, 2010
    Publication date: September 30, 2010
    Inventors: Keiichi YOSHIZUMI, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
  • Patent number: 7759763
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
  • Patent number: 7480164
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 20, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Publication number: 20080211029
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Application
    Filed: May 6, 2008
    Publication date: September 4, 2008
    Inventors: Keiichi YOSHIZUMI, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
  • Patent number: 7393737
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: July 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
  • Publication number: 20080049480
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Application
    Filed: October 15, 2007
    Publication date: February 28, 2008
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Patent number: 7317627
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: January 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Publication number: 20070211508
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Application
    Filed: May 8, 2007
    Publication date: September 13, 2007
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Patent number: 7233511
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: June 19, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Publication number: 20070069326
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Application
    Filed: August 8, 2006
    Publication date: March 29, 2007
    Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
  • Publication number: 20060274015
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Application
    Filed: August 14, 2006
    Publication date: December 7, 2006
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Patent number: 7110274
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: September 19, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Patent number: 6898096
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: May 24, 2005
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota
  • Publication number: 20040239655
    Abstract: A voltage level shift circuit is provided on a power IC manufactured with a high-voltage process instead of on a source driver IC with a large capacity display memory manufactured with a low-voltage fine wiring process. This makes it possible to reduce the cost of manufacturing a source driver IC and decrease the chip area, leading to reduction in the overall IC chip cost.
    Type: Application
    Filed: April 27, 2004
    Publication date: December 2, 2004
    Inventors: Kunihiko Tani, Takayuki Nakaji, Kazuhisa Higuchi, Yasushi Nagata
  • Publication number: 20020145599
    Abstract: There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages are determined accordingly. A semiconductor integrated circuit with a built-in power supply circuit, wherein a negative voltage generated in a power supply circuit is applied to a substrate or a well region as a bias voltage, is provided with a switch for temporarily applying the ground potential to the substrate or well region to be biased with the negative voltage at the time of starting up the power supply circuit.
    Type: Application
    Filed: March 7, 2002
    Publication date: October 10, 2002
    Inventors: Kazuya Endo, Naoki Miyamoto, Toshio Mizuno, Takayuki Nakaji, Takatoshi Uchida, Kazuo Ookado, Yoshikazu Yokota