Patents by Inventor Takayuki Nishiura

Takayuki Nishiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8133815
    Abstract: Compound-semiconductor-substrate polishing methods, compound semiconductor substrates, compound-semiconductor-epitaxial-substrate manufacturing methods, and compound semiconductor epitaxial substrates whereby oxygen superficially present on the substrates reduced. A compound semiconductor-substrate polishing method includes a preparation step (S10), a first polishing step (S20), and a second polishing step (S30). In the preparation step (S10), a compound semiconductor substrate is prepared. In the first polishing step (S20), the compound semiconductor substrate is polished with a chloric polishing agent. In the second polishing step (S30), subsequent to the first polishing step (S20), a polishing operation utilizing an alkaline aqueous solution containing an inorganic builder and having pH of 8.5 to 13.0 inclusive is performed.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 13, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshio Mezaki, Takayuki Nishiura, Masahiro Nakayama
  • Patent number: 8115927
    Abstract: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: February 14, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Takayuki Nishiura, Keiji Ishibashi
  • Patent number: 8044493
    Abstract: A GaAs semiconductor substrate includes a main surface (10m) having an inclined angle of 6° to 16° with respect to a (100) plane (10a), and a concentration of chlorine atoms on the main surface (10m) is not more than 1×1013 cm?2. Further, a method of manufacturing a GaAs semiconductor substrate includes a polishing step of polishing a GaAs semiconductor wafer, a first cleaning step of cleaning the polished GaAs semiconductor wafer, an inspection step of inspecting a thickness and a main surface flatness of the GaAs semiconductor wafer subjected to the first cleaning, and a second cleaning step of cleaning the inspected GaAs semiconductor wafer with one of an acid other than hydrochloric acid and an alkali.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: October 25, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takayuki Nishiura
  • Patent number: 7960284
    Abstract: Affords a III-V compound semiconductor substrate manufacturing method that enables enhancement of the substrate PL intensity. In such a III-V compound semiconductor substrate manufacturing method, first, the surface 3a of a wafer 3 is polished (polishing step). Second, the surface 3a of the wafer 3 is cleaned (first cleaning step S7). Next, the surface 3a of the wafer 3 is subjected to first dry-etching, employing a halogen-containing gas, while first bias voltage is applied to a chuck 24 for carrying the wafer 3. Subsequently, the surface 3a of the wafer 3 is subjected to second dry-etching, employing the halogen-containing gas (second dry-etching step S11), while second bias power lower than the first bias power is applied to the chuck 24.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: June 14, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Naoki Matsumoto, Takayuki Nishiura
  • Publication number: 20110018105
    Abstract: There is provided a method of producing a nitride-based compound semiconductor device that suppresses the adhesion of foreign matters including impurity, fine particles and the like on a surface of a compound semiconductor. The method of producing a nitride-based compound semiconductor device in accordance with the present invention includes the steps of: preparing a nitride-based compound semiconductor (or a substrate preparation step); and cleaning. In the step of cleaning, the nitride-based compound semiconductor is cleaned with a cleaning liquid having a pH of 7.1 or higher ultrasonically.
    Type: Application
    Filed: September 24, 2010
    Publication date: January 27, 2011
    Inventors: Akihiro Hachigo, Takayuki Nishiura
  • Patent number: 7854804
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1-d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: December 21, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Patent number: 7851381
    Abstract: A surface treatment method for a nitride crystal is a surface treatment method of chemically and mechanically polishing a surface of the nitride crystal. Oxide abrasive grains are used. The abrasive grains have a standard free energy of formation of at least ?850 kJ/mol as a converted value per 1 mole of oxygen molecules and have a Mohs hardness of at least 4. The surface treatment method efficiently provides, for efficiently obtaining a nitride crystal substrate that can be used for a semiconductor device, the nitride crystal having the smooth and high-quality surface formed thereon.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: December 14, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Takayuki Nishiura, Masato Irikura, Seiji Nakahata
  • Publication number: 20100248478
    Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.
    Type: Application
    Filed: June 7, 2010
    Publication date: September 30, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takayuki NISHIURA, Keiji Ishibashi
  • Publication number: 20100227532
    Abstract: A method of surface treatment of a Group III nitride crystal film includes polishing a surface of the Group III nitride crystal film, wherein a pH value x and an oxidation-reduction potential value y (mV) of a polishing liquid used for the polishing satisfy both relationships of y??50x+1,000 and y??50x+1,900.
    Type: Application
    Filed: April 28, 2010
    Publication date: September 9, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Takayuki Nishiura
  • Patent number: 7737043
    Abstract: There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semiconductor substrate, and a method of producing a compound semiconductor crystal. In the inspection method of the surface of the compound semiconductor substrate, the surface roughness Rms of the compound semiconductor substrate is measured using an atomic force microscope at the pitch of not more than 0.4 nm in a scope of not more than 0.2 ?m square. The surface roughness Rms of the compound semiconductor substrate measured by the inspection method is not more than 0.2 nm.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: June 15, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takayuki Nishiura, So Tanaka, Yusuke Horie, Kyoko Okita, Takatoshi Okamoto
  • Publication number: 20100123168
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Application
    Filed: December 10, 2009
    Publication date: May 20, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji ISHIBASHI, Tokiko KAJI, Seiji NAKAHATA, Takayuki NISHIURA
  • Patent number: 7713844
    Abstract: A method for working a nitride semiconductor substrate, comprising the steps of: preparing a disk-shaped nitride semiconductor substrate comprising a plurality of striped regions having defect concentration regions in which crystal defect density is higher than in surrounding low defect regions; and forming a cut-out at a specific location along the edge of the nitride semiconductor substrate, using as a reference the direction in which at least one from among the plurality of striped regions extends.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: May 11, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takayuki Nishiura, Yoshio Mezaki
  • Publication number: 20100068834
    Abstract: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement.
    Type: Application
    Filed: November 20, 2009
    Publication date: March 18, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Takayuki Nishiura, Keiji Ishibashi
  • Publication number: 20090291567
    Abstract: There is provided a cleaning method and production method that suppresses the adhesion of foreign matters including impurity, fine particles and the like on a surface of a compound semiconductor. A method of cleaning a nitride-based compound semiconductor in accordance with the present invention includes the steps of: preparing a nitride-based compound semiconductor (or a substrate preparation step); and cleaning. In the step of cleaning, a cleaning liquid having a pH of 7.1 or higher is used to clean the nitride-based compound semiconductor.
    Type: Application
    Filed: August 3, 2009
    Publication date: November 26, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: AKIHIRO HACHIGO, TAKAYUKI NISHIURA
  • Patent number: 7619301
    Abstract: A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle ? by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: November 17, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takayuki Nishiura, Yoshio Mezaki, Yusuke Horie, Yasuaki Higuchi
  • Publication number: 20090249747
    Abstract: Affords a compound semiconductor substrate packaging method for preventing oxidation of the surface of compound semiconductor substrates.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 8, 2009
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takayuki Nishiura, Yoshio Mezaki, Yoshiki Yabuhara
  • Patent number: 7569493
    Abstract: There is provided a cleaning method and production method that suppresses the adhesion of foreign matters including impurity, fine particles and the like on a surface of a compound semiconductor. A method of cleaning a nitride-based compound semiconductor in accordance with the present invention includes the steps of: preparing a nitride-based compound semiconductor (or a substrate preparation step); and cleaning. In the step of cleaning, a cleaning liquid having a pH of 7.1 or higher is used to clean the nitride-based compound semiconductor.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: August 4, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akihiro Hachigo, Takayuki Nishiura
  • Publication number: 20090159845
    Abstract: The present polishing slurry is a polishing slurry for chemically mechanically polishing a surface of a GaxIn1-xAsyP1-y crystal (0?x?1, 0?y?1), characterized in that this polishing slurry contains abrasive grains formed of SiO2, this abrasive grain is a secondary particle in which a primary particle is associated, and a ratio d2/d1 of an average particle diameter d2 of a secondary particle to an average particle diameter d1 of a primary particle is not less than 1.6 and not more than 10. According to such the polishing slurry, a crystal surface having a small surface roughness can be formed on a GaxIn1-xAsyP1-y crystal at a high polishing rate and effectively.
    Type: Application
    Filed: February 20, 2009
    Publication date: June 25, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji ISHIBASHI, Takayuki NISHIURA
  • Publication number: 20090140390
    Abstract: A GaAs semiconductor substrate includes a main surface (10m) having an inclined angle of 6° to 16° with respect to a (100) plane (10a), and a concentration of chlorine atoms on the main surface (10m) is not more than 1×1013 cm?2. Further, a method of manufacturing a GaAs semiconductor substrate includes a polishing step of polishing a GaAs semiconductor wafer, a first cleaning step of cleaning the polished GaAs semiconductor wafer, an inspection step of inspecting a thickness and a main surface flatness of the GaAs semiconductor wafer subjected to the first cleaning, and a second cleaning step of cleaning the inspected GaAs semiconductor wafer with one of an acid other than hydrochloric acid and an alkali.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 4, 2009
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Takayuki NISHIURA
  • Patent number: 7507668
    Abstract: The present polishing slurry is a polishing slurry for chemically mechanically polishing a surface of a GaxIn1?xAsyP1?y crystal (0?x?1, 0?y?1), characterized in that this polishing slurry contains abrasive grains formed of SiO2, this abrasive grain is a secondary particle in which a primary particle is associated, and a ratio d2/d1 of an average particle diameter d2 of a secondary particle to an average particle diameter d1 of a primary particle is not less than 1.6 and not more than 10. According to such the polishing slurry, a crystal surface having a small surface roughness can be formed on a GaxIn1?xAsyP1?y crystal at a high polishing rate and effectively.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: March 24, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Takayuki Nishiura