Abstract: Voltage converters are arranged in units of columns in a memory device. Each voltage converter is connected to a column decoder. The column decoder receives a column address signal and supplies a column selection signal to the voltage converter. The voltage converters apply a ground level voltage to the source junctions of the drive transistor pairs of the memory cells of the selected columns, and a voltage higher than the ground level voltage to the source junctions of the drive transistor pairs of the memory cells of the nonselected columns so as to decrease power consumption in the nonselected columns as compared with that in the selected columns.

Abstract: A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.

Abstract: A memory cell array consists of a plurality of memory sections. A pair of bit lines are provided for each column, and word lines are provided each for each row in each memory section. One end of the current path of a first transistor is connected to the corresponding bit line. A predetermined voltage is applied to the other end of the current path of the first transistor. One end of the current path of a second transistor is connected to the corresponding bit line. A predetermined voltage is applied to the other end of the current path of the first transistor. The current capacity of the first transistor is larger than that of the second transistor. After an address signal varies and a predetermined period elapses, the first transistor in the selected section turns on, the second transistor in the selected section turns off, the first transistor in the nonselected section turns off, and the second transistors in the nonselected section turns on.

Abstract: There is disclosed a sense amplifier characterized by comprising a pull-up circuit. The pull-up circuit comprises a first transistor arranged between the first of a pair of output nodes and a pull-up power source potential node, and a second transistor arranged between the second of the pair of output nodes and the pull-up power source potential node. The gate of the first transistor is connected to the second output node and the gate of the second transistor is connected to the first output node.

Abstract: A signal input circuit particularly well suited for use in MOS integrated circuits. The signal input circuit includes: and input gate circuit for receiving an input signal and an enable control signal, and for generating an output signal equal to the input signal when the enable control signal is in an "enable" state, and for providing a high output impedance when the enable control signal is in a "disable" state; and a holding circuit coupled to an output of the input gate circuit and to receiving the enable control signal, for holding, during the disable state, the output state of the input gate circuit immediately before the enable control signal changes to a disable state, the output impedance being high when the enable control signal is in an enable state.

Abstract: In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.

Abstract: A transition detector circuit comprises a first invertor train comprising 2n stages of invertors (n: positive integer including zero), the input thereof being connected to a signal input terminal while the output thereof is connected to an in-phase output terminal, a second invertor train comprising 2n+1 stages of invertors, the input thereof being connected to the signal input terminal, while the output thereof is connected to an antiphase output terminal, a third invertor train comprising at least one stage of an invertor, which is connected to the output of the first invertor train, a fourth invertor train, comprising at least one stage of an invertor, which is connected to the output of the second invertor train, and a fifth invertor train comprising at least one stage of an invertor, which is connected to the signal input terminal.