Patents by Inventor Takayuki Okamura
Takayuki Okamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10492294Abstract: A printed wiring board includes: an insulating base material; a first conductive layer disposed on a main surface of the insulating base material in a first region and a second region defined on a plane along the main surface; a second conductive layer disposed on a main surface of the first conductive layer in the first region; and an insulating layer disposed on the main surface of the first conductive layer in the second region. The ratio of a first evaluation value E1 to a second evaluation value E2 is 0.91 or more and 0.99 or less. The first evaluation value E1 is an evaluation value of strength of a first laminated part in the first region and the second evaluation value E2 is an evaluation value of strength of a second laminated part in the second region.Type: GrantFiled: October 12, 2016Date of Patent: November 26, 2019Assignee: FUJIKURA LTD.Inventors: Yasuo Fukuda, Takayuki Okamura
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Publication number: 20180324943Abstract: A printed wiring board includes: an insulating base material; a first conductive layer disposed on a main surface of the insulating base material in a first region and a second region defined on a plane along the main surface; a second conductive layer disposed on a main surface of the first conductive layer in the first region; and an insulating layer disposed on the main surface of the first conductive layer in the second region. The ratio of a first evaluation value E1 to a second evaluation value E2 is 0.91 or more and 0.99 or less. The first evaluation value E1 is an evaluation value of strength of a first laminated part in the first region and the second evaluation value E2 is an evaluation value of strength of a second laminated part in the second region.Type: ApplicationFiled: October 12, 2016Publication date: November 8, 2018Applicant: FUJIKURA LTD.Inventors: Yasuo Fukuda, Takayuki Okamura
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Patent number: 9583629Abstract: According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.Type: GrantFiled: November 25, 2015Date of Patent: February 28, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Jun Nishimura, Nobuaki Yasutake, Takayuki Okamura
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Patent number: 9368196Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on a side surface thereof: a first insulating film provided on a side surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on a side surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.Type: GrantFiled: December 22, 2014Date of Patent: June 14, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kei Sakamoto, Takayuki Okamura, Nobuaki Yasutake, Jun Nishimura
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Publication number: 20160079436Abstract: According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.Type: ApplicationFiled: November 25, 2015Publication date: March 17, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jun NISHIMURA, Nobuaki YASUTAKE, Takayuki OKAMURA
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Patent number: 9184217Abstract: According to one embodiment, a memory device includes: a first interconnect extending in a first direction; a plurality of second interconnects extending in a second direction intersecting with the first direction, and having lower ends positioned on the first interconnect; a plurality of third interconnects extending in a third direction intersecting with the second direction; a memory layer provided between the second interconnects and the third interconnects; and selectors respectively provided between the first interconnect and the lower ends of the plurality of second interconnects.Type: GrantFiled: September 10, 2013Date of Patent: November 10, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Nobuaki Yasutake, Takayuki Okamura
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Patent number: 9142288Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.Type: GrantFiled: December 8, 2014Date of Patent: September 22, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kei Sakamoto, Masaki Kondo, Nobuaki Yasutake, Takayuki Okamura
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Publication number: 20150255510Abstract: According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.Type: ApplicationFiled: August 18, 2014Publication date: September 10, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Jun Nishimura, Nobuaki Yasutake, Takayuki Okamura
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Patent number: 9111858Abstract: A non-volatile semiconductor memory device includes a cell array layer including a first wire, one or more memory cells stacked on the first wire, and a second wire formed on the memory cell so as to cross the first wire, wherein the memory cell includes a current rectifying element and a variable resistance element, and an atomic composition ratio of nitrogen is higher than that of oxygen in a part of a sidewall of the current rectifying element.Type: GrantFiled: March 15, 2013Date of Patent: August 18, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Jun Nishimura, Nobuaki Yasutake, Kei Sakamoto, Takayuki Okamura
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Publication number: 20150124516Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on a side surface thereof: a first insulating film provided on a side surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on a side surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.Type: ApplicationFiled: December 22, 2014Publication date: May 7, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kei SAKAMOTO, Takayuki OKAMURA, Nobuaki YASUTAKE, Jun NISHIMURA
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Publication number: 20150092473Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.Type: ApplicationFiled: December 8, 2014Publication date: April 2, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kei SAKAMOTO, Masaki KONDO, Nobuaki YASUTAKE, Takayuki OKAMURA
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Publication number: 20150085562Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.Type: ApplicationFiled: December 4, 2014Publication date: March 26, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi SONEHARA, Takayuki OKAMURA, Takashi SHIGEOKA, Masaki KONDO
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Patent number: 8937830Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on aside surface thereof: a first insulating film provided on aside surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on aside surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.Type: GrantFiled: February 27, 2013Date of Patent: January 20, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kei Sakamoto, Takayuki Okamura, Nobuaki Yasutake, Jun Nishimura
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Patent number: 8923031Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.Type: GrantFiled: February 27, 2013Date of Patent: December 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kei Sakamoto, Masaki Kondo, Nobuaki Yasutake, Takayuki Okamura
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Patent number: 8907318Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.Type: GrantFiled: October 31, 2012Date of Patent: December 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Sonehara, Takayuki Okamura, Takashi Shigeoka, Masaki Kondo
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Publication number: 20140312295Abstract: According to one embodiment, a memory device includes: a first interconnect extending in a first direction; a plurality of second interconnects extending in a second direction intersecting with the first direction, and having lower ends positioned on the first interconnect; a plurality of third interconnects extending in a third direction intersecting with the second direction; a memory layer provided between the second interconnects and the third interconnects; and selectors respectively provided between the first interconnect and the lower ends of the plurality of second interconnects.Type: ApplicationFiled: September 10, 2013Publication date: October 23, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Nobuaki YASUTAKE, Takayuki OKAMURA
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Patent number: 8791552Abstract: A semiconductor memory device includes a cell array layer including a first wire, a memory cell stacked on the first wire, and a second wire formed on the memory cell. The memory cell includes a variable resistance element and a current control element The current control element includes a first conductivity-type semiconductor into which a first impurity is doped, an i-type semiconductor in contact with the first conductivity-type semiconductor, a second conductivity-type semiconductor into which a second impurity is doped, and an impact ionization acceleration unit being formed between the i-type semiconductor and one of the first conductivity-type semiconductor and the second conductivity-type semiconductor.Type: GrantFiled: March 27, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Jun Nishimura, Nobuaki Yasutake, Takayuki Okamura
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Publication number: 20140003128Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.Type: ApplicationFiled: February 27, 2013Publication date: January 2, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kei SAKAMOTO, Masaki KONDO, Nobuaki YASUTAKE, Takayuki OKAMURA
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Publication number: 20140003127Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on aside surface thereof: a first insulating film provided on aside surface of the current rectifier element and the variable resistance element and having a composition ratio of anon-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on aside surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.Type: ApplicationFiled: February 27, 2013Publication date: January 2, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kei Sakamoto, Takayuki Okamura, Nobuaki Yasutake, Jun Nishimura
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Patent number: 8598649Abstract: A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.Type: GrantFiled: June 2, 2010Date of Patent: December 3, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Okamura, Noboru Ooike, Wataru Sakamoto, Takashi Izumida