Patents by Inventor Takayuki Onda
Takayuki Onda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8847301Abstract: A first connection portion and a second connection portion connect a first control gate to a second control gate, and are separated from each other. The first control gate includes a first disconnection portion between the first connection portion and a source diffusion layer closest to the first connection portion. The second control gate includes a second disconnection portion between the second connection portion and the source diffusion layer closest to the second connection portion. A first word gate and a second word gate are not disconnected in portions overlapping the first disconnection portion and the second disconnection portion.Type: GrantFiled: February 21, 2012Date of Patent: September 30, 2014Assignee: Renesas Electronics CorporationInventor: Takayuki Onda
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Publication number: 20130313624Abstract: A first connection portion and a second connection portion connect a first control gate to a second control gate, and are separated from each other. The first control gate includes a first disconnection portion between the first connection portion and a source diffusion layer closest to the first connection portion. The second control gate includes a second disconnection portion between the second connection portion and the source diffusion layer closest to the second connection portion. A first word gate and a second word gate are not disconnected in portions overlapping the first disconnection portion and the second disconnection portion.Type: ApplicationFiled: February 21, 2012Publication date: November 28, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Takayuki Onda
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Patent number: 8058162Abstract: A method of manufacturing a nonvolatile semiconductor memory includes: forming an insulator structure on a semiconductor substrate in a first region; forming a first gate insulating film on the semiconductor substrate outside the first region; blanket depositing a first gate material film and etching-back the first gate material film to form a first gate electrode on the first gate insulating film lateral to the insulator structure; removing the insulator structure; blanket forming a second gate insulating film; blanket depositing a second gate material film and etching-back the second gate material film to form a second gate electrode on the second gate insulating film in the first region; and silicidation of upper surfaces of the first and second gate electrodes. Any one of the first and second gate insulating films is a charge trapping film.Type: GrantFiled: April 7, 2010Date of Patent: November 15, 2011Assignee: Renesas Electronics CorporationInventor: Takayuki Onda
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Patent number: 7960777Abstract: A mask ROM is provided with a plurality of memory cells each including first and second nodes, and a transistor having a source and drain connected to the first and second nodes, respectively. A first memory cell out of the plurality of memory cells further includes a first resistive interconnection which provides an electrical connection between the first and second nodes. The resistance of the first resistive interconnection is adjusted depending on data stored onto the first memory cell.Type: GrantFiled: October 2, 2008Date of Patent: June 14, 2011Assignee: Renesas Electronics CorporationInventor: Takayuki Onda
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Publication number: 20100255670Abstract: A method of manufacturing a nonvolatile semiconductor memory includes: forming an insulator structure on a semiconductor substrate in a first region; forming a first gate insulating film on the semiconductor substrate outside the first region; blanket depositing a first gate material film and etching-back the first gate material film to form a first gate electrode on the first gate insulating film lateral to the insulator structure; removing the insulator structure; blanket forming a second gate insulating film; blanket depositing a second gate material film and etching-back the second gate material film to form a second gate electrode on the second gate insulating film in the first region; and silicidation of upper surfaces of the first and second gate electrodes. Any one of the first and second gate insulating films is a charge trapping film.Type: ApplicationFiled: April 7, 2010Publication date: October 7, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: TAKAYUKI ONDA
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Publication number: 20090090957Abstract: A mask ROM is provided with a plurality of memory cells each including first and second nodes, and a transistor having a source and drain connected to the first and second nodes, respectively. A first memory cell out of the plurality of memory cells further includes a first resistive interconnection which provides an electrical connection between the first and second nodes. The resistance of the first resistive interconnection is adjusted depending on data stored onto the first memory cell.Type: ApplicationFiled: October 2, 2008Publication date: April 9, 2009Applicant: NEC Electronics CorporationInventor: Takayuki Onda
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Publication number: 20050196905Abstract: A semiconductor device includes a semiconductor substrate, and an oxide layer formed thereon. The oxide layer has a window which is formed by forming a peeling-prevention layer on the oxide layer, forming a KrF-ray sensitive photoresist layer on the peeling-prevention layer, forming an opening in the KrF-ray sensitive photoresist layer, performing an anisotropic etching process by using the KrF-ray sensitive photoresist layer as a mask, so that an opening and a recess are respectively formed in the peeling-prevention layer and the oxide layer, and performing a wet etching process by using the peeling-prevention layer as a mask, resulting in formation of the recess of the oxide layer as the window in the oxide layer, whereby a surface area of the semiconductor substrate is exposed by the window.Type: ApplicationFiled: February 18, 2005Publication date: September 8, 2005Applicant: NEC ELECTRONICS CORPORATIONInventor: Takayuki Onda
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Patent number: 5639522Abstract: Disclosed is a side protective moulding having a decorative section and a rib section. The decorative section has a protruding section protruding most with respect to a door, and a curved section extending aslant from the protruding section toward the door. The rib section has a hollow section formed on the back side of the protruding section and a reinforcing leg section extending from the hollow section toward the door. The side moulding is moulded by a hollow injection moulding process. Adopting this moulding process can improve the outside appearance of the side moulding by eliminating sink marks and wrinkles from the surface of the decorative section if a thick wall section for increasing side moulding rigidity and impact strength is formed on the back side of the decorative section.Type: GrantFiled: July 25, 1995Date of Patent: June 17, 1997Assignee: Tokai Kogyo Co., Ltd.Inventors: Renji Maki, Katsuyuki Amano, Takayuki Onda, Kenji Hamabe, Osamu Aoki
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Patent number: 5574087Abstract: A molded protective strip for automobiles is prepared by the gas injection molding of a resin composition which comprises (A) 55 to 75% by weight of polypropylene, (B) 18 to 30% by weight of ethylene-propylene copolymer rubber, and (C) 10 to 20% by weight of talc, has a ratio (MI).sub.PP /(MI).sub.EPR of 10 or less, and a polydispersity index of 20 to 100. (MI).sub.PP and (MI).sub.EPR represents melt indices of the polypropylene of component (A) and the ethylene-propylene copolymer rubber of component (B), respectively. The polydispersity index is calculated from a frequency-storage modulus curve obtained with a composition consisting of components (A), (B), and (C) alone at the temperature of 230.degree. C. The molded protective strip can be prepared without using a vinyl chloride resin, shows almost no heat shrinkage, has a small coefficient of linear expansion, is excellent in dimensional stability, and exhibits excellent appearance.Type: GrantFiled: March 29, 1995Date of Patent: November 12, 1996Assignees: Idemitsu Petrochemical Co., Ltd., Honda Giken Kogyo Kabushiki KaishaInventors: Yutaka Kobayashi, Takayuki Onda, Kenji Hamabe, Osamu Aoki
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Patent number: 5480932Abstract: A polypropylene resin composition comprising: (a) 50 to 90% by weight of polypropylene, (b) 50 to 10% by weight of an ethylene-.alpha.-olefin copolymer elastomer having a Mooney viscosity (ML 1+4 (100.degree. C.)) of 10 to 100, (c) 0.5 to 10 parts by weight per 100 parts by weight of the total of the amounts of the components (a) and (b) of a linear olefinic polymer containing hydroxyl group which is liquid at room temperature, and (d) 0.5 to 15 parts by weight per 100 parts by weight of the total of the amounts of the components (a) and (b) of a linear olefinic polymer having a melting point of about 70.degree. to about 90.degree. C. and a number-average molecular weight of 1500 to 6000 and containing hydroxyl group or carbonyl group; and a protective strip for automobiles using the polypropylene resin composition are disclosed. Coating immediately after degreasing is made possible and excellent property for coating can be provided by using the polypropylene resin composition.Type: GrantFiled: June 27, 1994Date of Patent: January 2, 1996Assignees: Idemitsu Petrochemical Co., Ltd., Honda Giken Kogyo Kabushiki KaishaInventors: Yutaka Kobayashi, Osamu Aoki, Kenji Hamabe, Atsushi Takeuchi, Takayuki Onda