Patents by Inventor Takayuki Ooshima

Takayuki Ooshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190061295
    Abstract: When a sealing layer is formed of a strip-like sealant on an inner surface of a tire, thickness variations of the sealing layer can be easily restrained. A sealing layer (17) is formed of a strip-like sealant (20) on an inner surface (5) of a tire (1). A pair of side surfaces (21) of the sealant (20) is located on both sides in a width direction (H) of the sealant (20) and is inclined toward the same side in the width direction (H) of the sealant (20) with respect to a thickness direction (R) of the sealant (20). The sealant (20) is spirally arranged on the inner surface (5) of the tire (1) with the adjacent side surfaces (21) of the sealant (20) being overlapped with each other, so that the sealing layer (17) is formed.
    Type: Application
    Filed: December 21, 2016
    Publication date: February 28, 2019
    Applicant: BRIDGESTONE CORPORATION
    Inventors: Takayuki OOSHIMA, Toshiki NAKAMURA
  • Publication number: 20150041883
    Abstract: An object of the present invention is to improve the ESD resistance of an electrostatic protection element. The essence of the basic idea resides in that an electrostatic protection element ESD is configured to include not a thyristor or an npn bipolar transistor, but a pnp bipolar transistor so as to be connected in parallel with a diode. In other words, the essence of the basic idea resides in that an electrostatic protection element ESD is constituted by a diode parasitically provided with a pnp bipolar transistor.
    Type: Application
    Filed: August 6, 2014
    Publication date: February 12, 2015
    Inventors: Hiroki Kimura, Youhei Yanagida, Kenji Miyakoshi, Tomoyuki Miyoshi, Takayuki Ooshima
  • Publication number: 20150028385
    Abstract: The disclosed lateral bipolar transistor is manufactured by a manufacturing process of self-alignedly implanting an impurity to a gate electrode and thermally diffusing the impurity to form a base layer and an emitter layer. The gate electrode is utilized as an independent fourth terminal in addition to base, emitter, and collector terminals, whereby hfe can be controlled and enhanced by a gate potential. Accordingly, the present invention can provide a bipolar transistor that is hardly affected by a manufacturing variation, or that can be corrected by the gate terminal, and that has a high gain.
    Type: Application
    Filed: July 29, 2014
    Publication date: January 29, 2015
    Inventors: Tomoyuki Miyoshi, Takayuki Ooshima, Youhei Yanagida
  • Publication number: 20140284714
    Abstract: Disclosed is a semiconductor device that includes a first MOS transistor having a predetermined size and a second MOS transistor having a lager size than the first MOS transistor. The first MOS transistor is divided into two or more sections, each paired with a corresponding section of the second MOS transistor to form a unit cell. As the unit cell is cyclically formed on a substrate, the current mirror ratio between the total size of the first MOS transistor and the total size of the second MOS transistor remains unaffected by the nonuniformity of position-dependent temperature distribution.
    Type: Application
    Filed: February 27, 2014
    Publication date: September 25, 2014
    Inventors: Kenji Miyakoshi, Youhei Yanagida, Hiroki Kimura, Takayuki Ooshima
  • Patent number: 8531177
    Abstract: A timing detection device includes a draw back amount acquiring unit and a detecting unit. The draw back amount acquiring unit is configured to acquire a draw back amount of a received signal with respect to a peak value of the signal. The detecting unit is configured to detect the timing at which the draw back amount acquired by the draw back amount acquiring unit has exceeded a constant value as the timing at which a value of the signal is switched.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: September 10, 2013
    Assignee: Yokogawa Electric Corporation
    Inventors: Noriaki Kihara, Shunsuke Hayashi, Kenji Habaguchi, Takayuki Ooshima
  • Publication number: 20110062943
    Abstract: A timing detection device includes a draw back amount acquiring unit and a detecting unit. The draw back amount acquiring unit is configured to acquire a draw back amount of a received signal with respect to a peak value of the signal. The detecting unit is configured to detect the timing at which the draw back amount acquired by the draw back amount acquiring unit has exceeded a constant value as the timing at which a value of the signal is switched.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 17, 2011
    Applicant: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Noriaki Kihara, Shunsuke Hayashi, Kenji Habaguchi, Takayuki Ooshima
  • Patent number: 7587693
    Abstract: A delay calculation apparatus is provided for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice. The delay calculation apparatus is composed of a storage unit storing a clock circuit delay library containing clock circuit delay data obtained by delay calculation of a clock circuit, and a delay calculation section performing delay calculation of a structured ASIC incorporating the clock circuit to thereby generate delay calculation result data of the structured ASIC. The delay calculation section is designed to obtain at least a portion of the clock circuit delay data from the clock circuit delay library, and to merge the obtained portion of the clock circuit delay data into the delay calculation result data.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: September 8, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takayuki Ooshima
  • Publication number: 20060247875
    Abstract: A delay calculation apparatus is provided for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice. The delay calculation apparatus is composed of a storage unit storing a clock circuit delay library containing clock circuit delay data obtained by delay calculation of a clock circuit, and a delay calculation section performing delay calculation of a structured ASIC incorporating the clock circuit to thereby generate delay calculation result data of the structured ASIC. The delay calculation section is designed to obtain at least a portion of the clock circuit delay data from the clock circuit delay library, and to merge the obtained portion of the clock circuit delay data into the delay calculation result data.
    Type: Application
    Filed: May 1, 2006
    Publication date: November 2, 2006
    Inventor: Takayuki Ooshima