Patents by Inventor Takayuki Shirai
Takayuki Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967135Abstract: A computer executes a display procedure of displaying a list of character strings registered in advance in response to a predetermined operation for data forming a part of a web page; and a storage procedure of storing a character string selected by a user from the list into a storage device in association with the data, to thereby achieve more efficient labeling of data.Type: GrantFiled: February 25, 2020Date of Patent: April 23, 2024Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Yoshinari Shirai, Yasue Kishino, Shin Mizutani, Takayuki Suyama
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Publication number: 20220385202Abstract: This power conversion device includes a magnetic core which has a gap formed by cutting out a part of an annular shape, a resin primary molded body configured to hold the magnetic core by covering a first end portion and a second end portion of the magnetic core that are arranged opposite to each other with the gap therebetween from outside of the magnetic core in a radial direction, and a resin secondary molded body which has an exposed portion in which a surface of a portion of the primary molded body that covers the first end portion and the second end portion is exposed, and contains the primary molded body.Type: ApplicationFiled: May 20, 2022Publication date: December 1, 2022Inventors: Takayuki SHIRAI, Takuya YAGI, Shinichiro HAYAKAWA
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Publication number: 20220181662Abstract: Provided are a fuel cell and a fuel cell system capable of suppressing deterioration of the electrolyte membrane by iron-based foreign substances with a simple structure. The fuel cell includes: a MEGA and a nitrate compound, wherein the MEGA has an electrolyte membrane, an anode catalyst layer disposed on one surface of the electrolyte membrane, a cathode catalyst layer disposed on the other surface of the electrolyte membrane, an anode gas diffusion layer disposed on a surface of the anode catalyst layer which is opposite to a surface of the anode catalyst layer on the electrolyte membrane side, and a cathode gas diffusion layer disposed on a surface of the cathode catalyst layer which is opposite to a surface of the cathode catalyst layer on the electrolyte membrane side, and wherein the nitrate compound is disposed in the MEGA.Type: ApplicationFiled: November 9, 2021Publication date: June 9, 2022Inventor: Takayuki SHIRAI
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Patent number: 10519565Abstract: A low-resistance p-type SiC single crystal containing no inclusions is provided. A method for producing a SiC single crystal in which a SiC seed crystal substrate is contacted with a Si—C solution having a temperature gradient such that a temperature of the Si—C solution decreases from an interior of the Si—C solution toward a surface of the Si—C solution, to grow the SiC single crystal, wherein the Si—C solution comprises Si, Cr, Al and B, and wherein the Al is comprised in the Si—C solution in an amount of 10 at % or greater, based on the total of the Si, Cr, Al and B, and the B is comprised in the Si—C solution in an amount of greater than 0.00 at % and no greater than 1.00 at %, based on the total of the Si, Cr, Al and B.Type: GrantFiled: May 11, 2017Date of Patent: December 31, 2019Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takayuki Shirai
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Patent number: 10415152Abstract: A p-type SiC single crystal having lower resistivity than the prior art is provided. This is achieved by a method for producing a SiC single crystal in which a SiC seed crystal substrate is contacted with a Si—C solution having a temperature gradient such that the temperature decreases from the interior toward the surface, to grow a SiC single crystal, the method comprising: using as the Si—C solution a Si—C solution containing Si, Cr and Al, wherein the Al content is 3 at % or greater based on the total of Si, Cr and Al; and contacting a (0001) face of the SiC seed crystal substrate with the Si—C solution to grow a SiC single crystal from the (0001) face.Type: GrantFiled: June 28, 2016Date of Patent: September 17, 2019Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takayuki Shirai
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Patent number: 10167570Abstract: A n-type SiC single crystal with low resistivity and low threading dislocation density is provided, which is achieved by a n-type SiC single crystal containing germanium and nitrogen, wherein the density ratio of the germanium and the nitrogen [Ge/N] satisfies the relationship 0.17<[Ge/N]<1.60.Type: GrantFiled: July 23, 2014Date of Patent: January 1, 2019Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takayuki Shirai
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Publication number: 20170327967Abstract: A low-resistance p-type SiC single crystal containing no inclusions is provided. A method for producing a SiC single crystal in which a SiC seed crystal substrate is contacted with a Si—C solution having a temperature gradient such that a temperature of the Si—C solution decreases from an interior of the Si—C solution toward a surface of the Si—C solution, to grow the SiC single crystal, wherein the Si—C solution comprises Si, Cr, Al and B, and wherein the Al is comprised in the Si—C solution in an amount of 10 at % or greater, based on the total of the Si, Cr, Al and B, and the B is comprised in the Si—C solution in an amount of greater than 0.00 at % and no greater than 1.00 at %, based on the total of the Si, Cr, Al and B.Type: ApplicationFiled: May 11, 2017Publication date: November 16, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takayuki SHIRAI
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Patent number: 9732436Abstract: Provided are an SiC single-crystal ingot containing an SiC single crystal having a low threading dislocation density and low resistivity; an SiC single crystal; and a production method for the SiC single crystal. The SiC single crystal ingot contains a seed crystal and a grown crystal grown by a solution process in which the seed crystal is the base point, the grown crystal of the SiC single crystal ingot containing a nitrogen density gradient layer in which the nitrogen content increases in the direction of growth from the seed crystal.Type: GrantFiled: April 16, 2013Date of Patent: August 15, 2017Assignee: Toyota Jidosha Kabushiki KaishaInventors: Takayuki Shirai, Katsunori Danno
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Patent number: 9732437Abstract: A low-resistance p-type SiC single crystal containing no inclusions is provided. This is achieved by a method for producing a SiC single crystal wherein a SiC seed crystal substrate 14 is contacted with a Si—C solution 24 having a temperature gradient in which the temperature falls from the interior toward the surface, to grow a SiC single crystal, and wherein the method comprises: using, as the Si—C solution, a Si—C solution containing Si, Cr and Al, wherein the Al content is 3 at % or greater based on the total of Si, Cr and Al, and making the temperature gradient y (° C./cm) in the surface region of the Si—C solution 24 satisfy the following formula (1): y?0.15789x+21.52632 (1) wherein x represents the Al content (at %) of the Si—C solution.Type: GrantFiled: August 12, 2015Date of Patent: August 15, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takayuki Shirai
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Patent number: 9702057Abstract: Provided is a method for producing an n-type SiC single crystal, whereby it is possible to grow an n-type SiC single crystal having a low resistivity at a high speed. A method for producing an n-type SiC single crystal by bringing a SiC seed crystal substrate into contact with a Si—C solution having such a temperature gradient that the temperature gradually decreases from the inside toward the surface, thereby achieving the crystal growth of the n-type SiC single crystal. The method involves adding a nitride to a raw material for forming the Si—C solution or to the Si—C solution.Type: GrantFiled: April 1, 2013Date of Patent: July 11, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takayuki Shirai
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Publication number: 20170009374Abstract: A p-type SiC single crystal having lower resistivity than the prior art is provided. This is achieved by a method for producing a SiC single crystal in which a SiC seed crystal substrate is contacted with a Si—C solution having a temperature gradient such that the temperature decreases from the interior toward the surface, to grow a SiC single crystal, the method comprising: using as the Si—C solution a Si—C solution containing Si, Cr and Al, wherein the Al content is 3 at % or greater based on the total of Si, Cr and Al; and contacting a (0001) face of the SiC seed crystal substrate with the Si—C solution to grow a SiC single crystal from the (0001) face.Type: ApplicationFiled: June 28, 2016Publication date: January 12, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takayuki SHIRAI
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Publication number: 20160208411Abstract: A n-type SiC single crystal with low resistivity and low threading dislocation density is provided, which is achieved by a n-type SiC single crystal containing germanium and nitrogen, wherein the density ratio of the germanium and the nitrogen [Ge/N] satisfies the relationship 0.17<[Ge/N]<1.60.Type: ApplicationFiled: July 23, 2014Publication date: July 21, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takayuki SHIRAI
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Publication number: 20160068993Abstract: A low-resistance p-type SiC single crystal containing no inclusions is provided. This is achieved by a method for producing a SiC single crystal wherein a SiC seed crystal substrate 14 is contacted with a Si—C solution 24 having a temperature gradient in which the temperature falls from the interior toward the surface, to grow a SiC single crystal, and wherein the method comprises: using, as the Si—C solution, a Si—C solution containing Si, Cr and Al, wherein the Al content is 3 at % or greater based on the total of Si, Cr and Al, and making the temperature gradient y (° C./cm) in the surface region of the Si—C solution 24 satisfy the following formula (1): y?0.15789x+21.52632 (1) wherein x represents the Al content (at %) of the Si—C solution.Type: ApplicationFiled: August 12, 2015Publication date: March 10, 2016Inventor: Takayuki SHIRAI
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Publication number: 20150299896Abstract: Provided is a method for producing an n-type SiC single crystal, whereby it is possible to grow an n-type SiC single crystal having a low resistivity at a high speed. A method for producing an n-type SiC single crystal by bringing a SiC seed crystal substrate into contact with a Si—C solution having such a temperature gradient that the temperature gradually decreases from the inside toward the surface, thereby achieving the crystal growth of the n-type SiC single crystal. The method involves adding a nitride to a raw material for forming the Si—C solution or to the Si—C solution.Type: ApplicationFiled: April 1, 2013Publication date: October 22, 2015Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takayuki SHIRAI
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Publication number: 20150191849Abstract: Provided are an SiC single-crystal ingot containing an SiC single crystal having a low threading dislocation density and low resistivity; an SiC single crystal; and a production method for the SiC single crystal. The SiC single crystal ingot contains a seed crystal and a grown crystal grown by a solution process in which the seed crystal is the base point, the grown crystal of the SiC single crystal ingot containing a nitrogen density gradient layer in which the nitrogen content increases in the direction of growth from the seed crystal.Type: ApplicationFiled: April 16, 2013Publication date: July 9, 2015Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takayuki SHIRAI, Katsunori DANNO
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Patent number: 8445951Abstract: A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate.Type: GrantFiled: February 28, 2012Date of Patent: May 21, 2013Assignee: Renesas Electronics CorporationInventors: Hiroshi Furuta, Takayuki Shirai, Shunsaku Naga
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Publication number: 20120153370Abstract: A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate.Type: ApplicationFiled: February 28, 2012Publication date: June 21, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi FURUTA, Takayuki Shirai, Shunsaku Naga
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Patent number: 8050108Abstract: Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit (24) is provided between each bit line (21) and each sense amplifier (26). In writeback, the switch circuits are turned on at staggered time points. In readout, the switch circuits are turned on to read memory cell data to the sense amplifiers while the sense amplifiers are turned off, and the switch circuits are then turned off once. After that, the sense amplifiers are turned on to amplify the read data. The switch circuits are subsequently divided into groups and turned on again to write back the data amplified by the sense amplifiers to the memory cells. The switch circuits are divided into groups to be turned on at staggered time points during the writeback, to thereby avoid concentration of the writeback current in one time period.Type: GrantFiled: November 3, 2009Date of Patent: November 1, 2011Assignee: Renesas Electronics CorporationInventors: Kenjiyu Shimogawa, Hiroshi Furuta, Shunsaku Naga, Takayuki Shirai
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Publication number: 20100213520Abstract: Provided is a semiconductor integrated circuit device including a capacitor element with an improved TDDB life. A semiconductor integrated circuit device (1) includes: a first electrode (4) including a first semiconductor layer which protrudes with respect to a plane of a substrate; a side surface insulating film (5) formed on at least a part of a side surface of the first electrode (4); an upper surface insulating film (6) formed on the first electrode (4) and the side surface insulating film (5); and a second electrode (7) which covers the side surface insulating film (5) and the upper surface insulating film (6). The first electrode (4), the side surface insulating film (5), and the second electrode (7) constitute a capacitor element. A thickness of the upper surface insulating film (6) between the first electrode (4) and the second electrode (7) is larger than a thickness of the side surface insulating film (5) between the first electrode (4) and the second electrode (7).Type: ApplicationFiled: February 3, 2010Publication date: August 26, 2010Applicant: NEC Electronics CorporationInventors: Hiroshi Furuta, Takayuki Shirai, Shunsaku Naga
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Publication number: 20100110814Abstract: Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit (24) is provided between each bit line (21) and each sense amplifier (26). In writeback, the switch circuits are turned on at staggered time points. In readout, the switch circuits are turned on to read memory cell data to the sense amplifiers while the sense amplifiers are turned off, and the switch circuits are then turned off once. After that, the sense amplifiers are turned on to amplify the read data. The switch circuits are subsequently divided into groups and turned on again to write back the data amplified by the sense amplifiers to the memory cells. The switch circuits are divided into groups to be turned on at staggered time points during the writeback, to thereby avoid concentration of the writeback current in one time period.Type: ApplicationFiled: November 3, 2009Publication date: May 6, 2010Inventors: Kenjiyu Shimogawa, Hiroshi Furuta, Shunsaku Naga, Takayuki Shirai