Patents by Inventor Takayuki Umemoto

Takayuki Umemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978786
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: May 7, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Patent number: 11979981
    Abstract: The wiring board according to the present disclosure includes: a first insulating layer including insulating particles; a plurality of first conductors located on the first insulating layer at an interval of a first distance from each other; a second conductor located on the first insulating layer at an interval of a second distance from the first conductor; and a second insulating layer located on the first insulating layer to cover the first conductor and the second conductors and including the insulating particles. When a boundary portion between the first insulating layer and the second insulating layer is viewed in cross-section in the thickness direction, the ratio of a first area occupied by the insulating particles in a first boundary portion including the first distance is higher than the ratio of a second area occupied by the insulating particles in a second boundary portion including the second distance.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: May 7, 2024
    Assignee: Kyocera Corporation
    Inventor: Takayuki Umemoto
  • Publication number: 20230418232
    Abstract: An arm wearable device including a case, a module which has a brittle member and is provided in the case, and a plurality of holding portions which holds the module in the case such that flexural deformation of the module is restricted to deformation where a virtual straight line extending in a longitudinal direction of the brittle member serves as a center line.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 28, 2023
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Hiroki IGI, Masataka IIDA, Takayuki UMEMOTO
  • Publication number: 20230104567
    Abstract: The wiring board according to the present disclosure includes: a first insulating layer including insulating particles; a plurality of first conductors located on the first insulating layer at an interval of a first distance from each other; a second conductor located on the first insulating layer at an interval of a second distance from the first conductor; and a second insulating layer located on the first insulating layer to cover the first conductor and the second conductors and including the insulating particles. When a boundary portion between the first insulating layer and the second insulating layer is viewed in cross-section in the thickness direction, the ratio of a first area occupied by the insulating particles in a first boundary portion including the first distance is higher than the ratio of a second area occupied by the insulating particles in a second boundary portion including the second distance.
    Type: Application
    Filed: February 18, 2021
    Publication date: April 6, 2023
    Applicant: KYOCERA Corporation
    Inventor: Takayuki UMEMOTO
  • Patent number: 10602622
    Abstract: A wiring board includes a first insulating layer including a surface having unevenness, a second insulating layer including a surface having unevenness, laminated on the first insulating layer, and made of the same insulating material as that of the first insulating layer, insulating particles contained in the first and second insulating layers at rate of 40 to 80 wt %, a first wiring conductor on a first underlying metal layer surface, and a second wiring conductor on a second underlying metal layer surface. A second level difference of the unevenness in a surface region of the second insulating layer under the second wiring conductor is smaller than a first level difference of the unevenness in a surface region of the first insulating layer under the first wiring conductor, and the second level difference is not more than ? of an average particle size of the insulating particles.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: March 24, 2020
    Assignee: KYOCERA Corporation
    Inventors: Masaaki Harazono, Takayuki Umemoto, Hidetoshi Yugawa
  • Patent number: 10306769
    Abstract: A wiring board includes an insulating layer made of an insulating resin containing inorganic insulating particles, a groove positioned in a surface of the insulating layer and including a wall surface being perpendicular to the surface of the insulating layer, and a wiring conductor filled in the groove, wherein a cross-section of the insulating resin and cross-sections of the inorganic insulating particles are exposed at the wall surface in flush with each other.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 28, 2019
    Assignee: KYOCERA CORPORATION
    Inventors: Masaaki Harazono, Takayuki Umemoto
  • Publication number: 20190132962
    Abstract: A wiring board includes a first insulating layer including a surface having unevenness, a second insulating layer including a surface having unevenness, laminated on the first insulating layer, and made of the same insulating material as that of the first insulating layer, insulating particles contained in the first and second insulating layers at rate of 40 to 80 wt %, a first wiring conductor on a first underlying metal layer surface, and a second wiring conductor on a second underlying metal layer surface. A second level difference of the unevenness in a surface region of the second insulating layer under the second wiring conductor is smaller than a first level difference of the unevenness in a surface region of the first insulating layer under the first wiring conductor, and the second level difference is not more than ? of an average particle size of the insulating particles.
    Type: Application
    Filed: September 13, 2018
    Publication date: May 2, 2019
    Applicant: KYOCERA Corporation
    Inventors: Masaaki Harazono, Takayuki Umemoto, Hidetoshi Yugawa
  • Publication number: 20180146558
    Abstract: A wiring board includes an insulating layer made of an insulating resin containing inorganic insulating particles, a groove positioned in a surface of the insulating layer and including a wall surface being perpendicular to the surface of the insulating layer, and a wiring conductor filled in the groove, wherein a cross-section of the insulating resin and cross-sections of the inorganic insulating particles are exposed at the wall surface in flush with each other.
    Type: Application
    Filed: September 26, 2017
    Publication date: May 24, 2018
    Applicant: KYOCERA Corporation
    Inventors: Masaaki HARAZONO, Takayuki UMEMOTO
  • Patent number: 9913372
    Abstract: The wiring board of the present disclosure includes an insulating layer, and a wiring conductor existing so as to be adjacent to both main surfaces of the insulating layer; the insulating layer includes at least two particle-containing resin layers containing insulating particles in an insulating resin, and a particle-free resin layer formed of an insulating resin; and the particle-free resin layer is interposed between the particle-containing resin layers.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: March 6, 2018
    Assignee: KYOCERA Corporation
    Inventors: Masaaki Harazono, Takayuki Umemoto
  • Publication number: 20170215277
    Abstract: The wiring board of the present disclosure includes an insulating layer, and a wiring conductor existing so as to be adjacent to both main surfaces of the insulating layer; the insulating layer includes at least two particle-containing resin layers containing insulating particles in an insulating resin, and a particle-free resin layer formed of an insulating resin; and the particle-free resin layer is interposed between the particle-containing resin layers.
    Type: Application
    Filed: January 24, 2017
    Publication date: July 27, 2017
    Applicant: KYOCERA Corporation
    Inventors: Masaaki HARAZONO, Takayuki UMEMOTO
  • Patent number: 8863377
    Abstract: According to one embodiment of the invention, a method for manufacturing a circuit board comprises covering with a metal layer a surface of a first resin layer including polyimide resin; forming a plurality of conductive layers arranged on the metal layer with the conductive layers apart from each other in a planer view; roughening surfaces of the conductive layers with an alkaline aqueous solution; and etching a part of the metal layer between the conductive layers in the planer view to expose the surface of the first resin layer after roughening the surfaces of the conductive layers.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: October 21, 2014
    Assignee: Kyocera Corporation
    Inventors: Masaaki Harazono, Takayuki Umemoto
  • Publication number: 20120047731
    Abstract: According to one embodiment of the invention, a method for manufacturing a circuit board comprises forming a plurality of electroplated layers arranged apart from each other in a planer view on an underlying layer, wherein each of the electroplated layers comprises a first layer formed on the underlying layer by direct current electroplating, a second layer formed on the first layer by periodic reverse electroplating and a third layer, which is the outermost layer of the electroplated layer, formed on the second layer by direct current electroplating; etching a portion of the underlying layer between the electroplated layers in the planer view; forming an insulating layer on the third layer; forming a penetrating hole through the insulating layer to expose a part of the third layer at the bottom surface of the penetrating hole; forming a sputtered layer on an inner wall surface and the bottom surface of the penetrating hole.
    Type: Application
    Filed: August 31, 2011
    Publication date: March 1, 2012
    Applicant: KYOCERA CORPORATION
    Inventors: Tomohisa Murakami, Takayuki Umemoto
  • Publication number: 20110314666
    Abstract: According to one embodiment of the invention, a method for manufacturing a circuit board comprises covering with a metal layer a surface of a first resin layer including polyimide resin; forming a plurality of conductive layers arranged on the metal layer with the conductive layers apart from each other in a planer view; roughening surfaces of the conductive layers with an alkaline aqueous solution; and etching a part of the metal layer between the conductive layers in the planer view to expose the surface of the first resin layer after roughening the surfaces of the conductive layers.
    Type: Application
    Filed: April 27, 2011
    Publication date: December 29, 2011
    Applicant: Kyocera Corporation
    Inventors: Masaaki Harazono, Takayuki Umemoto
  • Patent number: 7802270
    Abstract: A disk reproducing apparatus with improved quality is provided which has a clamper and a clamper plate. By providing the clamp plate with connection portions radially extending from a radially inner peripheral portion toward radially outer peripheral portion of the clamp plate, the axial displacement relative to a clamp holder can be increased as compared to that in the existing structure. Moreover, by disposing the clamper on the radially inner peripheral portion of the clamp plate so as to be elastically deformable, the spacing in clamping can be increased to a drive part.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: September 21, 2010
    Assignee: Fujitsu Ten Limited
    Inventors: Kouichi Ogawa, Susumu Yamamoto, Takayuki Umemoto, Takeshi Fujii
  • Publication number: 20070220402
    Abstract: Embodiments in accordance with the present invention provide an auxiliary storage device that prevents performance degradation and collects data useful for buffer failure analysis. In one embodiment, a data set including user data and cyclic redundancy check (CRC) information is temporarily stored in a buffer. If a CRC error is detected in a data set that is read from the buffer during a data write or data read, the contents of the data set and the affected buffer address are recorded on a nonvolatile recording medium. Further, the buffer address is disabled. This makes it possible to store the data for reproducing a soft error that occurs in the buffer and prevent the performance of the auxiliary storage device from being degraded by a buffer error.
    Type: Application
    Filed: January 10, 2007
    Publication date: September 20, 2007
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Eiji Hagi, Takeshi Shikama, Takayuki Umemoto, Akira Kojima
  • Publication number: 20070169140
    Abstract: A disk reproducing apparatus with improved quality is provided which has a clamper and a clamper plate. By providing the clamp plate with connection portions radially extending from a radially inner peripheral portion toward radially outer peripheral portion of the clamp plate, the axial displacement relative to a clamp holder can be increased as compared to that in the existing structure. Moreover, by disposing the clamper on the radially inner peripheral portion of the clamp plate so as to be elastically deformable, the spacing in clamping can be increased to a drive part.
    Type: Application
    Filed: January 16, 2007
    Publication date: July 19, 2007
    Inventors: Kouichi Ogawa, Susumu Yamamoto, Takayuki Umemoto, Takeshi Fujii
  • Patent number: 6940684
    Abstract: When a head passes over a track with a projected item in a seek operation, the CPU delays a seek start time to conduct the seek by changing a period of time from a seek start position to a position of the track with a projected item. Or, the CPU conducts seek control by changing a speed table. Or, the CPU changes a sequence of items of a tag queue to obtain a seek locus not passing the projected item. By the control operation, a seek error due to thermal asperity is prevented and the head is not damaged. This also prevents appearance of a new projected item produced by contact between the magneto-resistive head and the projected item on the recording medium.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: September 6, 2005
    Assignee: Hitachi Global Storage Technologies Japan, Ltd.
    Inventors: Masaki Yoshioka, Kenichi Masuda, Yuji Hata, Takeshi Nakazawa, Takayuki Umemoto
  • Publication number: 20030193855
    Abstract: When a head passes over a track with a projected item in a seek operation, the CPU delays a seek start time to conduct the seek by changing a period of time from a seek start position to a position of the track with a projected item. Or, the CPU conducts seek control by changing a speed table. Or, the CPU changes a sequence of items of a tag queue to obtain a seek locus not passing the projected item. By the control operation, a seek error due to thermal asperity is prevented and the head is not damaged. This also prevents appearance of a new projected item produced by contact between the magneto-resistive head and the projected item on the recording medium.
    Type: Application
    Filed: February 24, 2003
    Publication date: October 16, 2003
    Inventors: Masaki Yoshioka, Kenichi Masuda, Yuji Hata, Takeshi Nakazawa, Takayuki Umemoto