Patents by Inventor Takeaki Komuro
Takeaki Komuro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9693069Abstract: It is an object of the present invention to provide an image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A block count determination part determines the number of intra macroblocks to be allocated in each frame. A position determination part arranges the intra macroblocks at random positions in each frame. A coding part performs coding on the basis of the number of intra macroblocks to be allocated in a time direction, which is determined by the block count determination part, and the arrangement of the intra macroblocks in a spatial direction, which is determined by the position determination part, to thereby output compressed image data.Type: GrantFiled: November 9, 2015Date of Patent: June 27, 2017Assignee: MegaChips CorporationInventors: Hiromu Hasegawa, Toshimitsu Tatsuka, Takeaki Komuro
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Patent number: 9661333Abstract: An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter for quantization. The controller determines a quantization parameter of a currently target macroblock as an increase or decrease from a reference value, and determines the increase or decrease based on a difference between a target amount of code for a predetermined number of macroblocks fewer than a total number of macroblocks within one frame and a generated amount of code of the predetermined number of macroblocks processed immediately before. The controller can further determine the increase or decrease, based on pixel information of the currently target macroblock such as an activity evaluation value.Type: GrantFiled: November 29, 2010Date of Patent: May 23, 2017Assignee: MegaChips CorporationInventors: Toshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada
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Patent number: 9532075Abstract: The image processor includes a ? multiplier circuit that approximately multiplies an input value X by ?. The ? multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register.Type: GrantFiled: March 19, 2014Date of Patent: December 27, 2016Assignee: MegaChips CorporationInventors: Takeaki Komuro, Nobuyuki Takasu, Kazuhiro Saito
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Publication number: 20160065971Abstract: It is an object of the present invention to provide an image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A block count determination part (12) determines the number of intra macroblocks to be allocated in each frame. A position determination part (13) arranges the intra macroblocks at random positions in each frame. A coding part (11) performs coding on the basis of the number of intra macroblocks to be allocated in a time direction, which is determined by the block count determination part (12), and the arrangement of the intra macroblocks in a spatial direction, which is determined by the position determination part (13), to thereby output compressed image data (22).Type: ApplicationFiled: November 9, 2015Publication date: March 3, 2016Applicant: MegaChips CorporationInventors: Hiromu HASEGAWA, Toshimitsu TATSUKA, Takeaki KOMURO
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Publication number: 20140286435Abstract: The image processor includes a ? multiplier circuit that approximately multiplies an input value X by ?. The ? multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register.Type: ApplicationFiled: March 19, 2014Publication date: September 25, 2014Applicant: MEGACHIPS CORPORATIONInventors: Takeaki KOMURO, Nobuyuki TAKASU, Kazuhiro SAITO
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Patent number: 8712176Abstract: An image processor that achieves reduction in delay amount, in comparison with code amount control GOP by GOP or frame by frame.Type: GrantFiled: November 29, 2010Date of Patent: April 29, 2014Assignee: MegaChips CorporationInventors: Toshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada
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Publication number: 20130195179Abstract: An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter in the quantization. The controller determines a quantization parameter of a currently target macroblock, based on a difference between a target amount of code for a specified number of macroblocks and an amount of code generated for a predetermined number of macroblocks processed immediately before. The controller variably sets the specified number.Type: ApplicationFiled: August 26, 2011Publication date: August 1, 2013Applicant: MegaChips CorporationInventors: Toshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada
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Publication number: 20130028534Abstract: An image processor that achieves reduction in delay amount, in comparison with code amount control GOP by GOP or frame by frame, is obtained.Type: ApplicationFiled: November 29, 2010Publication date: January 31, 2013Applicant: MegaChips CorporationInventors: Toshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada
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Publication number: 20120307881Abstract: A device preventing degradation of image quality caused by coding of a moving image. A compression coder performs compression coding on image data of respective pictures constituting an input moving image to generate inter-coded data or intra-coded data, and outputs the coded data to a wire or wireless transmission line. In a case of causing the compression coder to generate the inter-coded data, a controller sets a code amount equal to or smaller than a maximum code amount given by a value obtained by multiplying an upper limit transmission rate of a transmission line and a permissible time allocated per picture based on a picture rate of the input moving image. Meanwhile, in a case of causing the compression coder to generate the intra-coded data, the controller sets a code amount larger than the maximum code amount and equal to or smaller than N-times (N is an integer equal to or larger than two) the maximum code amount.Type: ApplicationFiled: November 9, 2010Publication date: December 6, 2012Applicant: MegaChips CorporationInventors: Takashi Sawada, Takeaki Komuro, Toshimitsu Tatsuka
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Publication number: 20120294361Abstract: An image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A block count determination part determines the number of intra macroblocks to be allocated in each frame. A position determination part arranges the intra macroblocks at random positions in each frame. A coding part performs coding on the basis of the number of intra macroblocks to be allocated in a time direction, which is determined by the block count determination part, and the arrangement of the intra macroblocks in a spatial direction, which is determined by the position determination part, to thereby output compressed image data.Type: ApplicationFiled: January 18, 2011Publication date: November 22, 2012Applicant: MegaChips CorporationInventors: Hiromu Hasegawa, Toshimitsu Tatsuka, Takeaki Komuro
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Publication number: 20120287990Abstract: An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter for quantization. The controller determines a quantization parameter of a currently target macroblock as an increase or decrease from a reference value, and determines the increase or decrease based on a difference between a target amount of code for a predetermined number of macroblocks fewer than a total number of macroblocks within one frame and a generated amount of code of the predetermined number of macroblocks processed immediately before. The controller can further determine the increase or decrease, based on pixel information of the currently target macroblock such as an activity evaluation value.Type: ApplicationFiled: November 29, 2010Publication date: November 15, 2012Applicant: MegaChips CorporationInventors: Toshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada