Patents by Inventor Takehiko Kawamura
Takehiko Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230275198Abstract: In a display device, the metal layer includes a plurality of openings, and electrode pads having an island shape overlap one or more of the plurality of openings via an insulating film including at least a flattening film.Type: ApplicationFiled: October 25, 2019Publication date: August 31, 2023Applicants: SHARP KABUSHIKI KAISHA, SHARP KABUSHIKI KAISHAInventors: JUNICHI YAMADA, TAKEHIKO KAWAMURA
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Patent number: 11322574Abstract: A display device including: a driver outside a display area; a special-shape portion on an edge of the display area, the special-shape portion being shaped like a line that is curved or oblique to an extension direction of signal lines in the display area; a plurality of first-type circuit blocks outside the special-shape portion, each of the first-type circuit blocks including a unit circuit for the driver in a rectangular region having a first side parallel to the extension direction and a second side perpendicular to, and shorter than, the first side; and a plurality of second-type circuit blocks outside the special-shape portion, each of the second-type circuit blocks including a unit circuit for the driver in a rectangular region obtained by rotating the previous rectangular region by 90°.Type: GrantFiled: April 12, 2018Date of Patent: May 3, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Takehiko Kawamura, Junichi Yamada, Makoto Yokoyama
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Publication number: 20210098560Abstract: A display device including: a driver outside a display area; a special-shape portion on an edge of the display area, the special-shape portion being shaped like a line that is curved or oblique to an extension direction of signal lines in the display area; a plurality of first-type circuit blocks outside the special-shape portion, each of the first-type circuit blocks including a unit circuit for the driver in a rectangular region having a first side parallel to the extension direction and a second side perpendicular to, and shorter than, the first side; and a plurality of second-type circuit blocks outside the special-shape portion, each of the second-type circuit blocks including a unit circuit for the driver in a rectangular region obtained by rotating the previous rectangular region by 90°.Type: ApplicationFiled: April 12, 2018Publication date: April 1, 2021Inventors: TAKEHIKO KAWAMURA, JUNICHI YAMADA, MAKOTO YOKOYAMA
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Patent number: 10698281Abstract: A liquid crystal display panel (100) according to the present invention includes a plurality of spacers configured to hold a gap between a first substrate (10) and a second substrate (30). The plurality of spacers include a plurality of first spacers in a display region and a plurality of second spacers (55) in a non-display region. The first substrate includes a first metal layer (12) and a second metal layer (16), a first transparent conductive layer (22) formed on the second metal layer and in direct contact with the second metal layer, a second inorganic insulating layer (23) formed on the first transparent conductive layer, and an organic insulating layer (25) formed on the second inorganic insulating layer. When viewed from the normal direction of the first substrate, each of the plurality of spacers overlaps with the first transparent conductive layer and the second inorganic insulating layer, and overlaps with the first metal layer and/or the second metal layer.Type: GrantFiled: January 13, 2017Date of Patent: June 30, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Junichi Morinaga, Masahiro Yoshida, Hidenobu Kimoto, Takehiko Kawamura
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Patent number: 10598993Abstract: Provided is a technique of suppressing display defects such as flicker, without limiting the arrangement of data lines, in a liquid crystal display device having a display area in a non-rectangular shape. A liquid crystal display device includes an active matrix substrate 10, a counter substrate, and a liquid crystal layer. The active matrix substrate 10 includes a plurality of gate lines 11, and a plurality of data lines 12. In each of pixels defined by the gate lines 11 and the data lines 12, a pixel electrode 14 is arranged, and in a display area R, common electrodes 15 are provided. Outside the display area R, capacitance-generating parts C that generate capacitances between some gate lines 11 among the plurality of gate lines 11 and the common electrode are provided. The some gate lines 11 have lengths smaller than the gate lines having the maximum length, and intersect with some data lines 12 among the plurality of data lines 12.Type: GrantFiled: July 10, 2017Date of Patent: March 24, 2020Assignee: Sharp Kabushiki KaishaInventors: Satoshi Horiuchi, Seijirou Gyouten, Sachio Tsujino, Takehiko Kawamura, Junichi Morinaga
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Publication number: 20190250478Abstract: Provided is a technique of suppressing display defects such as flicker, without limiting the arrangement of data lines, in a liquid crystal display device having a display area in a non-rectangular shape. A liquid crystal display device includes an active matrix substrate 10, a counter substrate, and a liquid crystal layer. The active matrix substrate 10 includes a plurality of gate lines 11, and a plurality of data lines 12. In each of pixels defined by the gate lines 11 and the data lines 12, a pixel electrode 14 is arranged, and in a display area R, common electrodes 15 are provided. Outside the display area R, capacitance-generating parts C that generate capacitances between some gate lines 11 among the plurality of gate lines 11 and the common electrode are provided. The some gate lines 11 have lengths smaller than the gate lines having the maximum length, and intersect with some data lines 12 among the plurality of data lines 12.Type: ApplicationFiled: July 10, 2017Publication date: August 15, 2019Applicant: Sharp Kabushiki KaishaInventors: Satoshi HORIUCHI, Seijirou GYOUTEN, Sachio TSUJINO, Takehiko KAWAMURA, Junichi MORINAGA
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Publication number: 20190033636Abstract: A liquid crystal display panel (100) according to the present invention includes a plurality of spacers configured to hold a gap between a first substrate (10) and a second substrate (30). The plurality of spacers include a plurality of first spacers in a display region and a plurality of second spacers (55) in a non-display region. The first substrate includes a first metal layer (12) and a second metal layer (16), a first transparent conductive layer (22) formed on the second metal layer and in direct contact with the second metal layer, a second inorganic insulating layer (23) formed on the first transparent conductive layer, and an organic insulating layer (25) formed on the second inorganic insulating layer. When viewed from the normal direction of the first substrate, each of the plurality of spacers overlaps with the first transparent conductive layer and the second inorganic insulating layer, and overlaps with the first metal layer and/or the second metal layer.Type: ApplicationFiled: January 13, 2017Publication date: January 31, 2019Inventors: JUNICHI MORINAGA, MASAHIRO YOSHIDA, HIDENOBU KIMOTO, TAKEHIKO KAWAMURA
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Publication number: 20190004357Abstract: A liquid crystal display panel includes: a first substrate; a second substrate; a liquid crystal layer provided between the first substrate and the second substrate; and a plurality of spacers configured to hold a gap between the first substrate and the second substrate. The first substrate includes: a plurality of TFTs; a plurality of first wiring lines including part of a first metal layer; a plurality of second wiring lines including part of a second metal layer; an inorganic insulating layer formed on the second metal layer; a first transparent conductive layer formed below the inorganic insulating layer; a second transparent conductive layer formed on the inorganic insulating layer; and an organic insulating layer formed on the inorganic insulating layer. Each of the plurality of spacers overlaps with at least one of a source electrode and a drain electrode of a corresponding one of the plurality of TFTs, and each of the plurality of spacers includes a part of the organic insulating layer.Type: ApplicationFiled: January 13, 2017Publication date: January 3, 2019Inventors: JUNICHI MORINAGA, HIDENOBU KIMOTO, MASAHIRO YOSHIDA, TAKEHIKO KAWAMURA
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Patent number: 9927658Abstract: An active matrix substrate for a liquid crystal panel of an FFS mode includes a plurality of connecting units in a connecting region in order to electrically connect a common electrode, a first common main wiring 31, and a second common main wiring 32. The connecting unit includes a contact hole 41 that connects a connecting electrode 37 and the first common main wiring 31, the connecting electrode 37 formed integrally with the common electrode, and a contact hole 42 that connects the connecting electrode 37 and the second common main wiring 32. An amorphous Si film 122 of the second common main wiring 32 is formed larger than a main conductor part 131 of the second common main wiring 32 in a position of the contact hole 41, and is covered with SiNx films 151, 152 that are protective insulating films. This prevents the connecting electrode from having a step disconnection at a pattern end of the common main wiring.Type: GrantFiled: June 24, 2015Date of Patent: March 27, 2018Assignee: Sharp Kabushiki KaishaInventors: Takehiko Kawamura, Tetsuya Tarui, Hidenobu Kimoto
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Publication number: 20170227799Abstract: An active matrix substrate for a liquid crystal panel of an FFS mode includes a plurality of connecting units in a connecting region in order to electrically connect a common electrode, a first common main wiring 31, and a second common main wiring 32. The connecting unit includes a contact hole 41 that connects a connecting electrode 37 and the first common main wiring 31, the connecting electrode 37 formed integrally with the common electrode, and a contact hole 42 that connects the connecting electrode 37 and the second common main wiring 32. An amorphous Si film 122 of the second common main wiring 32 is formed larger than a main conductor part 131 of the second common main wiring 32 in a position of the contact hole 41, and is covered with SiNx films 151, 152 that are protective insulating films. This prevents the connecting electrode from having a step disconnection at a pattern end of the common main wiring.Type: ApplicationFiled: June 24, 2015Publication date: August 10, 2017Inventors: Takehiko KAWAMURA, Tetsuya TARUI, Hidenobu KIMOTO
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Patent number: 9299877Abstract: An active matrix substrate (2) is provided with first connecting wirings (641, 643, 645, 647) connected to gate terminals (51) to which extraction wirings (611, 613, 615, 617) are connected, second connecting wirings (642, 644, 646) connected to gate terminals (51) to which extraction wirings (612, 614, 616) are connected, bundled wirings (651 to 654) each composed of a mutually adjacent first connecting wiring and second connecting wiring bundled together, a first inspection wiring (66) capable of inputting an inspection signal to bundled wirings (652, 654) that are not adjacent to each other among the bundled wirings, and a second inspection wiring (67) capable of inputting an inspection signal to bundled wirings (651, 653) that are not adjacent to each other and not connected to the first inspection wiring (66) among the bundled wirings.Type: GrantFiled: July 12, 2013Date of Patent: March 29, 2016Assignee: Sharp Kabushiki KaishaInventors: Masahiro Yoshida, Takehiko Kawamura, Katsuhiro Okada
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Publication number: 20140078423Abstract: A liquid crystal panel (a liquid crystal element) 12 according to the present invention includes a pair of substrates 12a and 12b having a normal distance therebetween, a liquid crystal layer 27 arranged between the substrates 12a and 12b, a plurality of first spacers 34, and a plurality of second spacers 35. The first spacers 34 have an average particle diameter AD1 that is larger than the normal distance SD between the substrates 12a and 12b and are configured to define a distance between the substrates 12a and 12b. The second spacers 35 have an average particle diameter AD2 that is smaller than the normal distance SD between the substrates 12a and 12b and are configured to define the distance between the substrates 12a and 12b.Type: ApplicationFiled: March 18, 2012Publication date: March 20, 2014Applicant: SHARP KABUSHIKI KAISHAInventors: Hidehiko Suzuki, Kazuhide Akita, Takehiko Kawamura, Hiroyuki Sone, Nobuhiro Waka, Tohru Shirai, Yuichi Sonoyama
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Patent number: 8653827Abstract: Provided is an active matrix substrate having improved display quality without forming an inspection line in a terminal arrangement region for inspecting short circuit between connection lines. Scanning lines (40) include first scanning lines having input ends for a scanning signal on one end side, and second scanning lines having input ends for a scanning signal the other end side. In a display region (4), the first scanning lines and the second scanning lines are formed alternately one by one. An active matrix substrate (2) includes a first inspection line (70) and a second inspection line (72) that cross each of a plurality of first connection lines (61), and a third inspection line (75) and a fourth inspection line (77) that cross each of a plurality of second connection lines (64). The first to the fourth inspection lines (70, 72, 75, 77) are formed in a frame-shaped wiring region (6), excluding the terminal arrangement region (5) and the display region (4).Type: GrantFiled: March 13, 2009Date of Patent: February 18, 2014Assignee: Sharp Kabushiki KaishaInventors: Kazunori Tanimoto, Isao Ogasawara, Masahiro Yoshida, Takehiko Kawamura, Hideaki Takizawa
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Publication number: 20130299850Abstract: An active matrix substrate (2) is provided with first connecting wirings (641, 643, 645, 647) connected to gate terminals (51) to which extraction wirings (611, 613, 615, 617) are connected, second connecting wirings (642, 644, 646) connected to gate terminals (51) to which extraction wirings (612, 614, 616) are connected, bundled wirings (651 to 654) each composed of a mutually adjacent first connecting wiring and second connecting wiring bundled together, a first inspection wiring (66) capable of inputting an inspection signal to bundled wirings (652, 654) that are not adjacent to each other among the bundled wirings, and a second inspection wiring (67) capable of inputting an inspection signal to bundled wirings (651, 653) that are not adjacent to each other and not connected to the first inspection wiring (66) among the bundled wirings.Type: ApplicationFiled: July 12, 2013Publication date: November 14, 2013Inventors: Masahiro YOSHIDA, Takehiko Kawamura, Katsuhiro Okada
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Patent number: 8582068Abstract: An active matrix substrate is provided with first inspection wirings (70, 75) capable of inputting inspection signals to first switching wirings that are not adjacent to each other among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other among the second switching wirings (69, 74), and second inspection wirings (72, 77) capable of inputting inspection signals to first switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the second switching wirings (69, 74).Type: GrantFiled: April 28, 2009Date of Patent: November 12, 2013Assignee: Sharp Kabushiki KaishaInventors: Takehiko Kawamura, Kazunori Tanimoto, Isao Ogasawara, Masahiro Yoshida, Hideaki Takizawa
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Patent number: 8502227Abstract: An active matrix substrate (2) is provided with first connecting wirings (641, 643, 645, 647) connected to gate terminals (51) to which extraction wirings (611, 613, 615, 617) are connected, second connecting wirings (642, 644, 646) connected to gate terminals (51) to which extraction wirings (612, 614, 616) are connected, bundled wirings (651 to 654) each composed of a mutually adjacent first connecting wiring and second connecting wiring bunched together, a first inspection wiring (66) capable of inputting an inspection signal to bunched wirings (652, 654) that are not adjacent to each other among the bundled wirings, and a second inspection wiring (67) capable of inputting an inspection signal to bundled wirings (651, 653) that are not adjacent to each other and not connected to the first inspection wiring (66) among the bundled wirings.Type: GrantFiled: May 11, 2009Date of Patent: August 6, 2013Assignee: Sharp Kabushiki KaishaInventors: Masahiro Yoshida, Takehiko Kawamura, Katsuhiro Okada
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Publication number: 20110127536Abstract: An active matrix substrate (2) is provided with first connecting wirings (641, 643, 645, 647) connected to gate terminals (51) to which extraction wirings (611, 613, 615, 617) are connected, second connecting wirings (642, 644, 646) connected to gate terminals (51) to which extraction wirings (612, 614, 616) are connected, bundled wirings (651 to 654) each composed of a mutually adjacent first connecting wiring and second connecting wiring bunched together, a first inspection wiring (66) capable of inputting an inspection signal to bunched wirings (652, 654) that are not adjacent to each other among the bundled wirings, and a second inspection wiring (67) capable of inputting an inspection signal to bundled wirings (651, 653) that are not adjacent to each other and not connected to the first inspection wiring (66) among the bundled wirings.Type: ApplicationFiled: May 11, 2009Publication date: June 2, 2011Inventors: Masahiro Yoshida, Takehiko Kawamura, Katsuhiro Okada
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Publication number: 20110018142Abstract: An active matrix substrate is provided with first inspection wirings (70, 75) capable of inputting inspection signals to first switching wirings that are not adjacent to each other among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other among the second switching wirings (69, 74), and second inspection wirings (72, 77) capable of inputting inspection signals to first switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the second switching wirings (69, 74).Type: ApplicationFiled: April 28, 2009Publication date: January 27, 2011Inventors: Takehiko Kawamura, Kazunori Tanimoto, Isao Ogasawara, Masahiro Yoshida, Hideaki Takizawa
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Publication number: 20110006780Abstract: Provided is an active matrix substrate having improved display quality without forming an inspection line in a terminal arrangement region for inspecting short circuit between connection lines. Scanning lines (40) include first scanning lines having input ends for a scanning signal on one end side, and second scanning lines having input ends for a scanning signal the other end side. In a display region (4), the first scanning lines and the second scanning lines are formed alternately one by one. An active matrix substrate (2) includes a first inspection line (70) and a second inspection line (72) that cross each of a plurality of first connection lines (61), and a third inspection line (75) and a fourth inspection line (77) that cross each of a plurality of second connection lines (64). The first to the fourth inspection lines (70, 72, 75, 77) are formed in a frame-shaped wiring region (6), excluding the terminal arrangement region (5) and the display region (4).Type: ApplicationFiled: March 13, 2009Publication date: January 13, 2011Inventors: Kazunori Tanimoto, Isao Ogasawara, Masahiro Yoshida, Takehiko Kawamura, Hideaki Takizawa
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Patent number: D956000Type: GrantFiled: November 29, 2019Date of Patent: June 28, 2022Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Kato, Shinichi Kato, Masashi Tsuru, Kenji Chimata, Yutaka Kinoshita, Koki Uchiyama, Tadashi Yato, Takahiro Kobayashi, Kota Araki, Takehiko Kawamura