Abstract: In a musical sound generator that generates plural element tones based on plural pieces of element data and generates a musical sound by combining the generated element tones, a selector selects, upon detecting a sound generation control event, one or more pieces of element data among the plural pieces of element data according to the sound generation control event and in the way corresponding to the sound generation type of each of the plural pieces of element data, and a generator generates, in accordance with each of the element data selected by the selector, an element tone having sound characteristics corresponding to the parameter included in the detected sound generation control event and the characteristic control data included in each of the selected element data.

Abstract: A clock recovery circuit comprises a phase comparator detecting phase differences between input data and sampling clocks and outputs them as pulse signals of two values of advanced and delayed, a low-pass filter reducing frequencies of the pulse signals outputted from the phase comparator and outputs reduced frequencies, a control signal generator monitoring the reduced frequencies and generates a phase control signal used to adjust the phase of each sampling clock to be small or large based on the ratio of the advanced and delayed signals, a phase interpolator adjusting the phase of each sampling clock upon receiving the phase control signal, and a frequency divider dividing the sampling clock having the adjusted phase by a predetermined frequency division ratio to output it, and controls the low-pass filter and control signal generator based on the frequency divided output.

Abstract: A clock recovery circuit comprises a phase comparator detecting phase differences between input data and sampling clocks and outputs them as pulse signals of two values of advanced and delayed, a low-pass filter reducing frequencies of the pulse signals outputted from the phase comparator and outputs reduced frequencies, a control signal generator monitoring the reduced frequencies and generates a phase control signal used to adjust the phase of each sampling clock to be small or large based on the ratio of the advanced and delayed signals, a phase interpolator adjusting the phase of each sampling clock upon receiving the phase control signal, and a frequency divider dividing the sampling clock having the adjusted phase by a predetermined frequency division ratio to output it, and controls the low-pass filter and control signal generator based on the frequency divided output.

Abstract: A voltage/current converting circuit whose gain is hard to be influenced by the fluctuation in process has a constant current source for generating a constant current; a shunt circuit for flowing the constant current generated by said constant current source to a first and second current paths, the first current path flowing a first current corresponding to an input voltage, and the second current path flowing a second current defined as a difference between the constant current and the first current; and an output circuit for taking out a current bearing a predetermined relationship with the first current.

Abstract: A phase synchronous circuit, in the process of locking an internal signal to an input signal by a PLL loop, makes a frequency of the internal signal stepwise approximate to a frequency of the input signal under digital PLL control at a first stage, and adjusting a phase under analog PLL control at a next stage, thus controlling a variable frequency oscillator at the two stages. A gain with which an analog PLL control system is burdened can be thereby reduced, and a gain of VCO may not be set larger than required even if a frequency of an output signal f.sub.out is high.

Abstract: The synchronous circuit adopts a differential signal propagation to reduce in-phase noise by restoring the charge loss caused by leak current. A synchronous circuit comprises: a comparing circuit (12) for comparing an input signal (IN) or a signal formed on the basis of the input signal with a feedback signal (OUT) or a signal formed on the basis of the feedback signal with respect to phase or frequency; a signal forming circuit (13) for forming a first and second output signals (13A and 13B) as a differential signal on the basis of the outputs (12A and 12B) of the comparing circuit; a filter circuit (14) for eliminating high frequency region noise of the first and second output signals (13A and 13B) outputted by the signal forming circuit; and an output circuit (15) for outputting the feedback signal (OUT) whose phase or frequency is adjusted according to a difference between the first and second output signals (14A and 14B) passed through the filter circuit.

Abstract: The synchronous circuit has: a phase comparator for comparing a feedback signal with an input reference signal to detect a phase difference and outputting a phase difference signal corresponding to the phase difference; a charge pump for outputting charge/discharge signals on the basis of the phase difference signal output from said phase comparator; a low-pass filter for changing a charge amount accumulated in a capacitor on the basis of the charge/discharge signals output from said charge pump and outputting control signals corresponding to the charge amount as differential signals; a voltage-controlled oscillator for changing an oscillation frequency of an output on the basis of the control signals output from said low-pass filter; a frequency divider for multiplying the output from said voltage-controlled oscillator and outputting the feedback signal; and fixing means arranged on an output side of said charge pump and operated, when the phase difference between the reference signal and the feedback signal

Abstract: A voltage controlled oscillator is capable of rectilinearly changing an oscillation frequency over a wide range while keeping, to a fixed value, a signal amplitude of a ring oscillator using an differential amplifier by eliminating dependency of the signal amplitude upon a tail current. A load resistor section of each delay element is constructed of a variable resistor element for changing a differential output current flowing corresponding to variations in tail current, and a clamp circuit for fixing the amplitude of an output terminal of the delay element.