Abstract: A lenticular lens medium forms a lenticular lens which includes a plurality of semicylindrical-shaped or arc-shaped elongated convex parts. The lenticular lens medium has a volume resistivity of 1×107-1×1014 ?·cm and a surface resistivity of 1×108-1×1015?/?.

Abstract: A lenticular lens medium forms a lenticular lens which comprises a plurality of semicylindrical-shaped or arc-shaped elongated convex parts. The lenticular lens medium has a volume resistivity of 1×107-1×1014?·cm and a surface resistivity of 1×108-1×1015?/?. The lenticular lens medium including the convex parts has a thickness of 0.3-3 mm.

Abstract: A lenticular lens medium forms a lenticular lens which comprises a plurality of semicylindrical-shaped or arc-shaped elongated convex parts. The lenticular lens medium has a volume resistivity of 1×107-1×1014 ?·cm and a surface resistivity of 1×108-1×1015 ?/?. The lenticular lens medium including the convex parts has a thickness of 0.3-3 mm.

Abstract: A lenticular lens medium forms a lenticular lens which includes a plurality of semicylindrical-shaped or arc-shaped elongated convex parts. The lenticular lens medium has a volume resistivity of 1×107-1×1014?·cm and a surface resistivity of 1×108-1×1015?/?.

Abstract: A test pattern includes a test wiring pattern on a lower surface of a substrate. First, second, third and fourth upper patterns are formed on an upper surface of the substrate. First, second, third and fourth electrodes are formed respectively on the first, second, third and fourth upper patterns. The first and second electrodes are for connection to first and second test probes. First and second via-holes are formed through the substrate respectively to connect the first and second upper patterns electrically to one end of the test wiring pattern. Third and fourth via-holes are formed through the substrate respectively to connect the third and fourth upper patterns electrically to another end of the test wiring pattern.

Abstract: A test pattern used for testing an electrical characteristic of a semiconductor substrate, includes: a first conductive pattern formed on a lower surface of the semiconductor substrate; a second conductive pattern formed on an upper surface of the semiconductor substrate; first and second electrodes formed on the second conductive pattern, the electrodes being connected to test probes; and a first test via-hole formed through the semiconductor substrate to connect the first and second conductive pattern electrically to each other.

Abstract: A test pattern for testing contact resistance of a subject via hole. The test pattern includes first and second conductive patterns respectively formed on lower and upper substrate surfaces and connected to the subject via hole. First and second electrodes are formed on the second conductive pattern. Third and fourth electrodes are formed on the substrate upper surface. First and second test via-holes are formed through the substrate to connect the first conductive pattern to the third electrode and the first conductive pattern to the fourth electrode, respectively. The first and third electrodes are connected to a current test probe so that a test current flows through the first electrode, the subject via hole, the test via-hole and then the third electrode. The second and fourth electrodes are connected to a voltage test probe so as that a test voltage is applied through the second electrode, the subject via hole, the second test via-hole and then the fourth electrode.

Abstract: A test pattern used for testing an electrical characteristic of a semiconductor substrate, includes: a first conductive pattern formed on a lower surface of the semiconductor substrate; a second conductive pattern formed on an upper surface of the semiconductor substrate; first and second electrodes formed on the second conductive pattern, the electrodes being connected to test probes; and a first test via-hole formed through the semiconductor substrate to connect the first and second conductive pattern electrically to each other.

Abstract: A test pattern used for testing an electrical characteristic of a semiconductor substrate, includes: a first conductive pattern formed on a lower surface of the semiconductor substrate; a second conductive pattern formed on an upper surface of the semiconductor substrate; first and second electrodes formed on the second conductive pattern, the electrodes being connected to test probes; and a first test via-hole formed through the semiconductor substrate to connect the first and second conductive pattern electrically to each other.

Abstract: A silicon oxide film formed on a compound semiconductor substrate is evaluated by estimating the quantity of silicon-silicon bonds operating as electron traps in the silicon oxide film from a peak with a wave number of 880/centimeter in the Fourier-transform infrared spectrum of the silicon oxide film. This peak, which is an indicator of silicon-silicon stretching vibration, provides an index of expected power performance degradation during operation of field-effect transistors incorporating the silicon oxide film as an interlayer. Power degradation can be reduced by fabricating the semiconductor device under conditions that reduce the estimated quantity of silicon-silicon bonds, without the need to measure the power degradation.

Abstract: In a semiconductor device, particles are removed from the surface of a gold conductive layer before an intermediate insulating layer of an amino silane compound is formed. An organic insulating layer is formed on the intermediate insulating layer. As a result, adhesion strength between the conductive layer and the intermediate insulating layer can be improved.

Abstract: A test pattern used for testing an electrical characteristic of a semiconductor substrate, includes: a first conductive pattern formed on a lower surface of the semiconductor substrate; a second conductive pattern formed on an upper surface of the semiconductor substrate; first and second electrodes formed on the second conductive pattern, the electrodes being connected to test probes; and a first test via-hole formed through the semiconductor substrate to connect the first and second conductive pattern electrically to each other.

Abstract: A silicon oxide film formed on a compound semiconductor substrate is evaluated by estimating the quantity of silicon-silicon bonds operating as electron traps in the silicon oxide film from a peak with a wave number of 880/centimeter in the Fourier-transform infrared spectrum of the silicon oxide film. This peak, which is an indicator of silicon-silicon stretching vibration, provides an index of expected power performance degradation during operation of field-effect transistors incorporating the silicon oxide film as an interlayer. Power degradation can be reduced by fabricating the semiconductor device under conditions that reduce the estimated quantity of silicon-silicon bonds, without the need to measure the power degradation.

Abstract: Particles are removed from a surface of a gold conductive layer before forming an intermediate insulating layer of an amino silane compound.

Abstract: A test pattern used for testing an electrical characteristic of a semiconductor substrate, includes: a first conductive pattern formed on a lower surface of the semiconductor substrate; a second conductive pattern formed on an upper surface of the semiconductor substrate; first and second electrodes formed on the second conductive pattern, the electrodes being connected to test probes; and a first test via-hole formed through the semiconductor substrate to connect the first and second conductive pattern electrically to each other.

Abstract: A surface treatment method for a GaAs substrate in which an oxide film on a surface of the GaAs substrate can be nitrided efficiently to form GaN. The surface treatment method includes a first process of forcedly oxidizing the surface of the GaAs substrate and a second process which, subsequently to the first process, washes the surface of the GaAs substrate with running water. The forced oxidation may be carried out by immersing the GaAs substrate in aqueous hydrogen peroxide solution or by treating the GaAs substrate by oxygen (O2) ashing.

Abstract: An electroplating apparatus is made up of a cup having a plating solution therein, a plating solution controlling unit which overflows the plating solution from the cup, a holding unit which holds an object to be plated so as to contact to the overflowed plating solution, and a mesh shaped anode electrode provided in an internal portion of the cup, the mesh shaped anode electrode having a surface comprising a metal which are plated by the plating solution. Accordingly, the electroplating apparatus can get the plated film having a smooth surface.