Patents by Inventor Takehiro Hasegawa

Takehiro Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7672164
    Abstract: A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: March 2, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takehiro Hasegawa, Akira Umezawa, Koji Sakui, Fumitaka Arai, Ryo Mitani
  • Publication number: 20100015596
    Abstract: A kit or an immuno-chromatographic test device for detection of respiratory syncytial virus (RSV), comprising at least an RSV F protein-recognizing anti-RSV monoclonal antibody produced by hybridoma RSF2-412. An anti-RSV monoclonal antibody recognizing an RS virus F protein, which is selected from the group consisting of an antibody produced by hybridoma RSF2-412, an antibody produced by hybridoma RSF1-1565, and an antibody produced by hybridoma RSF6-255.
    Type: Application
    Filed: July 17, 2009
    Publication date: January 21, 2010
    Applicant: SYSMEX CORPORATION
    Inventors: Ayumi ASAEDA, Naoya Okitsu, Hiroshi Kumamoto, Kouji Sakaguchi, Takehiro Hasegawa
  • Publication number: 20090315418
    Abstract: A structure and method for holding an electric wire connected to the inside of an electric compressor incorporating a motor. The structure has a holding member for holding an electric wire present between a connection terminal section for connection to the outside and a built-in electric device. The structure and method can reliably eliminate possibility of adverse affection to an input electric wire caused by vibration, etc. while preventing a reduction in efficiency of assembly work and an increase in size of the compressor.
    Type: Application
    Filed: June 20, 2007
    Publication date: December 24, 2009
    Inventor: Takehiro Hasegawa
  • Publication number: 20090269221
    Abstract: An electric compressor having a built-in electric motor for driving the compressor and in which a connection section between an external terminal for power supply to the electric motor and the end of a wire from a stator of the electric motor is stored in a compressor housing. The electric compressor is characterized in that the connection section is constructed from a housing side coupler engaged with the compressor housing, a power supply-external terminal side coupler engaged with the housing side coupler, and a stator side coupler for holding the end of the wire from the stator, fitted to the power supply-external terminal side coupler, and engaged with the housing side coupler. In this electric compressor, vibration resistance of a terminal connection section for the motor is improved and breakage and momentary electrical interruption at the terminal connection section can be prevented, with productivity of the compressor maintained at a good level.
    Type: Application
    Filed: December 27, 2006
    Publication date: October 29, 2009
    Inventor: Takehiro Hasegawa
  • Publication number: 20090129954
    Abstract: An electric compressor incorporating an electric motor for driving a compression mechanism and containing, in a compressor housing, a joint between an external terminal for supplying power to the electric motor and an end of a wire from a stator of the electric motor. The electric compressor has a vibration proof means mechanically preventing at least one of disconnection, electrical instantaneous interruption, and damage on an insulating member that are caused by vibration at the joint and/or the vicinity of the joint. The vibration proof means can adopt various structures. When such a mechanical vibration proof means is provided in the electric compressor, vibration proof performance can be enhanced at the joint of a motor terminal with good productivity achieved, and occurrence of disconnection and instantaneous interruption of the terminal joint can be prevented.
    Type: Application
    Filed: May 2, 2006
    Publication date: May 21, 2009
    Inventor: Takehiro Hasegawa
  • Publication number: 20090087926
    Abstract: The invention provides an immunochromatographic test device for detecting a test substance in a sample, comprising a chromatographic membrane carrier; a sample developing member; and a labeling substance holding member; wherein a substance being capable of reacting to a human anti-mouse antibody is held in a member disposed at a position which is more upstream on the basis of the sample developing direction than the chromatographic membrane carrier, as well as an a method for detecting a test substance in a sample by using an immunochromatographic test device and a method for manufacturing an immunochromatographic test device.
    Type: Application
    Filed: August 13, 2008
    Publication date: April 2, 2009
    Applicant: SYSMEX CORPORATION
    Inventors: Takehiro HASEGAWA, Masumi Murakami, Takeshi Imoarai
  • Publication number: 20080212373
    Abstract: A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.
    Type: Application
    Filed: February 7, 2008
    Publication date: September 4, 2008
    Inventors: Takehiro HASEGAWA, Akira Umezawa, Koji Sakui, Fumitaka Arai, Ryo Mitani
  • Patent number: 7344400
    Abstract: A terminal connection structure of a motor incorporated within a compressor for connecting feed terminals for a stator of a motor to the compressor includes a lid, which is attached to a compressor body portion for securing external feed terminals with a hermetic seal. The terminal connection structure is provided with a resin chamber on an inner surface of the lid, through which the external feed terminals extend, and a resin housing containing wire-side terminals, which are provided at ends of wires connected to the stator and which are connected to the external feed terminals. In the structure, superior insulation properties may be obtained even if the compressor size is reduced, and the productivity and assembling performance of the compressor may be improved.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: March 18, 2008
    Assignee: Sanden Corporation
    Inventor: Takehiro Hasegawa
  • Patent number: 7339828
    Abstract: A semiconductor device comprises a memory cell array and a source line driver. Each of the memory cells in the memory cell array has a floating gate cell transistor which stores data by accumulating charge in the floating gate and a select gate transistor whose drain is connected to the source of the cell transistor and whose source is connected to a source line. The source line driver is configured so as to drive the source line in a write operation at a potential between the substrate bias potential of the cell transistor and select gate transistor and the ground potential.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: March 4, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takehiro Hasegawa, Susumu Shuto
  • Patent number: 7332766
    Abstract: A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: February 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takehiro Hasegawa, Akira Umezawa, Koji Sakui, Fumitaka Arai, Ryo Mitani
  • Patent number: 7312503
    Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge accumulation layer and a control gate. The second MOS transistor has one end of its current path connected to one end of a current path of the first MOS transistor. The local bit line connects other end of the current paths of the first MOS transistors. The first switch element makes a connection between the local bit lines and the global bit line. The holding circuit is connected to the global bit line and holds data to be written into the memory cells.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: December 25, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Umezawa, Takehiro Hasegawa
  • Patent number: 7281910
    Abstract: A motor driven compressor having a motor for driving a compression mechanism includes a connecting portion for connecting between an external terminal for supplying electricity to the motor and a wire end portion of a stator of the motor. The connecting portion is located above the motor and the compression mechanism. Further, the connecting portion is formed on the stator housing which accommodates the motor and the stator. The connecting portion is disposed in a hollow projection portion, which extends upward from the housing. Accordingly, the motor driven compressor which is readily manufactured, may avoid a leakage current by insulating a terminal portion of the motor from the housing of compressor.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: October 16, 2007
    Assignee: Sanden Corporation
    Inventor: Takehiro Hasegawa
  • Patent number: 7245530
    Abstract: A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: July 17, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Ichikawa, Takehiro Hasegawa, Akira Umezawa, Takuya Fujimoto
  • Publication number: 20060237798
    Abstract: A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.
    Type: Application
    Filed: June 20, 2006
    Publication date: October 26, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takehiro Hasegawa
  • Patent number: 7091564
    Abstract: A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takehiro Hasegawa
  • Publication number: 20060148097
    Abstract: A test strip for immunochromatography comprising a sample receiving member, a label holding member, and a chromatography membrane is described. The chromatography membrane has a first detection zone and a second detection zone. The second detection zone is formed by utilizing a blocking material and the second substance. A method for producing above the test strip is also described.
    Type: Application
    Filed: January 5, 2006
    Publication date: July 6, 2006
    Inventors: Haruki Yamaguchi, Takehiro Hasegawa, Takeshi Imoarai
  • Publication number: 20060083066
    Abstract: A semiconductor device comprises a memory cell array and a source line driver. Each of the memory cells in the memory cell array has a floating gate cell transistor which stores data by accumulating charge in the floating gate and a select gate transistor whose drain is connected to the source of the cell transistor and whose source is connected to a source line. The source line driver is configured so as to drive the source line in a write operation at a potential between the substrate bias potential of the cell transistor and select gate transistor and the ground potential.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 20, 2006
    Inventors: Takehiro Hasegawa, Susumu Shuto
  • Publication number: 20060068626
    Abstract: A terminal connection structure of a motor incorporated within a compressor for connecting feed terminals for a stator of a motor to the compressor includes a lid, which is attached to a compressor body portion for securing external feed terminals with a hermetic seal. The terminal connection structure is provided with a resin chamber on an inner surface of the lid, through which the external feed terminals extend, and a resin housing containing wire-side terminals, which are provided at ends of wires connected to the stator and which are connected to the external feed terminals. In the structure, superior insulation properties may be obtained even if the compressor size is reduced, and the productivity and assembling performance of the compressor may be improved.
    Type: Application
    Filed: September 20, 2005
    Publication date: March 30, 2006
    Inventor: Takehiro Hasegawa
  • Patent number: 6994530
    Abstract: A vibration type compressor related to the present invention, in which a compressor main body 3 is built into a gastight vessel 2 including a yoke 7-1, a magnetic path member 7 formed from a column-shaped core pole 7-2, a permanent magnet 12 arranged in the magnetic path, an electromagnetic coil 14 which is arranged within an annular magnetic gap 13 between the magnetic path members 7 by being supported by a mechanical vibration system to as to be able to vibrate and is wound around a lead plate to perform the connection treatment of a terminal thereof, a piston 16 connected to the electromagnetic coil 14, and a cylinder block 8 which closes the yoke 7-1 and in the interior of which is formed the cylinder portion 17 housing the piston 16, characterized in that the permanent magnet 12 is formed from a neodymium magnet or a rare-earth magnet and in that the cylindrical permanent magnet 12 is divided into four parts in the axial direction thereof, the four-part divided magnet being bonded and fixed to the side o
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: February 7, 2006
    Assignee: Sawafuji Electric Co., Ltd.
    Inventors: Yoshiaki Fujisawa, Takehiro Hasegawa
  • Publication number: 20050237808
    Abstract: A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.
    Type: Application
    Filed: April 22, 2005
    Publication date: October 27, 2005
    Inventors: Masaki Ichikawa, Takehiro Hasegawa, Akira Umezawa, Takuya Fujimoto