Abstract: According to one embodiment, a LSI design apparatus includes a first logic synthesis portion executing a design of a LSI in a logic gate level, a extraction portion extracting paths from the LSI, a determination portion determining a character of each of the paths, a parameter setting portion setting an upper limit of a transition time of a signal on each of the paths independently based on the character of each of the paths, and a second logic synthesis portion revising the design of the LSI generated in the first logic synthesis portion by optimizing each of the paths so that each of the paths satisfies the upper limit of the transition time of the signal.

Abstract: The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.

Abstract: Systems and methods for the implementation of more efficient cache locking mechanisms are disclosed. These systems and methods may alleviate the need to present both a virtual address (VA) and a physical address (PA) to a cache mechanism. A translation table is utilized to store both the address and the locking information associated with a virtual address, and this locking information is passed to the cache along with the address of the data. The cache can then lock data based on this information. Additionally, this locking information may be used to override the replacement mechanism used with the cache, thus keeping locked data in the cache. The translation table may also store translation table lock information such that entries in the translation table are locked as well.

Abstract: A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

Abstract: Systems and methods for determining whether to retire a data entry from a buffer using multiple retirement logic units. In one embodiment, each retirement unit concurrently evaluates retirement conditions for one of the buffer entries in an associated subset (e.g., even or odd) of the buffer. Selection logic coupled to the retirement units alternately selects the first or second retirement unit for retirement of one of the entries in the associated subset. Because the aggregate number of entries retired by the combined retirement logic units is divided by the number of retirement logic units, each retirement logic unit has more time to process the retirement conditions for corresponding queue entries. The buffer may be any of a variety of different types of buffers and may comprise a single buffer, or multiple buffers.

Abstract: Systems and methods for the implementation of more efficient cache locking mechanisms are disclosed. These systems and methods may alleviate the need to present both a virtual address (VA) and a physical address (PA) to a cache mechanism. A translation table is utilized to store both the address and the locking information associated with a virtual address, and this locking information is passed to the cache along with the address of the data. The cache can then lock data based on this information. Additionally, this locking information may be used to override the replacement mechanism used with the cache, thus keeping locked data in the cache. The translation table may also store translation table lock information such that entries in the translation table are locked as well.

Abstract: Systems and methods for bypassing lower level caches and enabling direct access to higher level caches in order to provide fixed data latency and increased amounts of immediately accessible storage. One embodiment comprises a memory system having multiple cache memories that have increasing data latencies and amounts of storage. In a first mode which is suitable to support a microprocessor mode of a dual-mode processor, each data access proceeds conventionally, with accesses to successively higher levels of cache memory. In a second mode which is suitable to support a DSP mode of the dual-mode processor, the memory system bypasses the lower level cache and directly accesses the higher level cache in order to achieve a fixed latency (with enough cache storage to be useful to operate the processor in a DSP mode.

Abstract: Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) which ensure testing of specific logic by forcing specific values into scan latches that contain otherwise pseudorandom test bit patterns. In one embodiment, an LBIST system comprises a plurality of scan latches and forcing logic coupled to a first set of the scan latches which provide inputs to selected target logic. The forcing logic is configured to overwrite values stored in the first set of scan latches with desired values. In one embodiment, the forcing logic includes a bypass path that enables shifting of unaltered bit patterns around the first set of scan latches. Bits in the bypass path may be inverted when the bypass path is not being used in order to help detect errors in the operation of the bypass path.

Abstract: A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present invention introduces a cache hit or cache miss input into the load/store dependency logic. If the incoming load operation is a cache hit, then the quadword boundary address value is used for detection. If the incoming load operation is a cache miss, then the cacheline boundary address value is used for detection. This invention enhances the performance of LHS and LHR operations in a memory system.

Abstract: A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

Abstract: The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.

Abstract: A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

Abstract: The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.

Abstract: Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) which ensure testing of specific logic by forcing specific values into scan latches that contain otherwise pseudorandom test bit patterns. In one embodiment, an LBIST system comprises a plurality of scan latches and forcing logic coupled to a first set of the scan latches which provide inputs to selected target logic. The forcing logic is configured to overwrite values stored in the first set of scan latches with desired values. In one embodiment, the forcing logic includes a bypass path that enables shifting of unaltered bit patterns around the first set of scan latches. Bits in the bypass path may be inverted when the bypass path is not being used in order to help detect errors in the operation of the bypass path.

Abstract: A system and method for determining whether to retire a data entry from a buffer. A portion of the retirement conditions is processed prior to the data entry being considered for retirement resulting in faster processing of remaining retirement conditions at the time retirement of the data is to be considered. The results from the pre-processing are stored as predecoded retirement information, which is later used with the remaining retirement conditions to determine whether the data is to be retired from the buffer.

Abstract: Systems and methods for bypassing lower level caches and enabling direct access to higher level caches in order to provide fixed data latency and increased amounts of immediately accessible storage. One embodiment comprises a memory system having multiple cache memories that have increasing data latencies and amounts of storage. In a first mode which is suitable to support a microprocessor mode of a dual-mode processor, each data access proceeds conventionally, with accesses to successively higher levels of cache memory. In a second mode which is suitable to support a DSP mode of the dual-mode processor, the memory system bypasses the lower level cache and directly accesses the higher level cache in order to achieve a fixed latency (with enough cache storage to be useful to operate the processor in a DSP mode.

Abstract: Systems and methods for determining whether to retire a data entry from a buffer using multiple retirement logic units. In one embodiment, each retirement unit concurrently evaluates retirement conditions for one of the buffer entries in an associated subset (e.g., even or odd) of the buffer. Selection logic coupled to the retirement units alternately selects the first or second retirement unit for retirement of one of the entries in the associated subset. Because the aggregate number of entries retired by the combined retirement logic units is divided by the number of retirement logic units, each retirement logic unit has more time to process the retirement conditions for corresponding queue entries. The buffer may be any of a variety of different types of buffers and may comprise a single buffer, or multiple buffers.

Abstract: Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to generate an address of the needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load and/or store instruction specifying the same address. If such a previous load/store instruction is found, the thread information is used to determine if the previous load/store instruction is from the same thread. If the previous load/store instruction is from the same thread, the cache hit signal is ignored, and the load instruction is stored in the queue. A load/store unit is also described.

Abstract: The present invention provides a method of updating the cache state information for store transactions in an system in which store transactions only read the cache state information upon entering the unit pipe or store portion of the store/load queue. In this invention, store transactions in the unit pipe and queue are checked whenever a cache line is modified, and their cache state information updated as necessary. When the modification is an invalidate, the check tests that the two share the same physical addressable location. When the modification is a validate, the check tests that the two involve the same data cache line.

Abstract: Systems and methods for determining dependencies between processor instructions in multiple phases. In one embodiment, a partial comparison is made between the addresses of a sequence of instructions. Younger instructions having potential dependencies on older instructions are suspended if the partial comparison yields a match. One or more subsequent comparisons are made for suspended instructions based on portions of the addresses referenced by the instructions that were not previously compared. If subsequent comparisons determine that the addresses of the instructions do not match, the suspended instructions are reinstated and execution of the suspended instructions is resumed. In one embodiment, data needed by suspended instructions is speculatively requested in case the instructions are reinstated.