Abstract: An interface control device controls the packet-type transfer of data between one or more computers and one or more input/output devices. According to one embodiment of the present invention, when the interface control device receives the lead packet in a series of packets from an input/output device, it creates new device control data to control the transfer of the series of packets, and also determines an identification number for the particular series of packet transfers. The interface control device then sends a notification packet, containing the identification number, to the sending input/output device in response to receiving the lead packet. When the interface control device receives a packet that is a second or subsequent packet in the series of packets, it determines whether the data stored in the packet are normal by referring to the device control data corresponding to the identification number stored in the subsequent packet.

Abstract: A programmable buffer circuit comprises a logical gate circuit having a second input terminal, a third input terminal and a first output terminal, and a first input terminal. The second input terminal is connected to the first input terminal. Further, a selective signal generating circuit for supplying two kinds of selective signals in logical level to the third input terminal is provided. A tri-state inverter circuit having a fourth input terminal and a second output terminal is provided and a tri-state buffer circuit having a fifth input terminal and a third output terminal is provided. The fourth input terminal and the fifth input terminal are connected to the first output terminal. A fourth output terminal is connected to the second output terminal and the third output terminal.

Abstract: A data processing system has a dynamic address translation function for dynamically translating virtual addresses into real addresses and processes data. The system employs a plurality of control registers for managing the developed addresses of address translation tables and a selector for selecting one of the control registers. The control register selected by the selector specifies one of the address translation tables, which is used to dynamically translate a virtual address into a real address.

Abstract: A semiconductor memory device having memory cells and digit lines connected to the memory cells, a precharger precharging the digit lines of the memory cells to a dropped voltage, a memory cell selector selecting one of the memory cell, a sense amplifier comparing a level of the digit line of the selected memory cell with a reference level to read out data. The dropped voltage is applied to the memory cells to disuse a current detection part of a conventional sense amplifier, resulting in miniaturization of the memory device.

Abstract: An I/O interface control method and data processing equipment each of which can avoid data destruction in an I/O unit even when a channel control unit is in a check/stop state. When an abnormal state notification signal from the channel control unit has been received, the channel element completes an I/O operation in execution to halt a transmission to a new I/O operation. When the abnormal state notification signal delayed by a predetermined time has been received, the main storage control unit separates the channel control unit from the channel element to halt the data transmission. The present invention can be applicable to computer systems each including a DASD acting as an I/O unit.