Patents by Inventor Takenao Nemoto
Takenao Nemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10553410Abstract: A method includes performing an etching process in a first process module, moving a workpiece formed by the etching process from the first process module to a second process module, and performing a film forming process on the workpiece in the second process module. In the performing the film forming process, an insulating film is formed on a first surface and a second surface of a laminated portion by plasma of a processing gas that contains hydrogen. In the performing the film forming process, an internal pressure of the second process module is 200 mTorr or more, and a hydrogen partial pressure of the second process module is 15 mTorr or less. The performing the etching process, the moving the workpiece, and the performing the film forming process are consistently performed in a state where oxygen is exhausted.Type: GrantFiled: September 2, 2016Date of Patent: February 4, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Yasuhiko Saito, Takenao Nemoto
-
Patent number: 9765430Abstract: A plasma processing apparatus for alternately performing a first plasma processing step using first and second processing gases and a second plasma processing step using third and fourth processing gases. The apparatus includes: a processing container that has a dielectric window in a ceiling and removably accommodates a workpiece; an exhaust unit that evacuates the processing container; a processing gas supply unit that supplies the first, second, third, and fourth processing gases into the processing container; a first gas introduction unit including a top plate gas injection port, a dielectric window gas flow path, and a first external gas flow path; a second gas introduction unit including a sidewall gas injection port, a sidewall gas flow path, and a second external gas flow path; an electromagnetic wave supply unit that supplies electromagnetic waves into the plasma generating space; a bypass exhaust path; and an opening/closing valve.Type: GrantFiled: February 23, 2015Date of Patent: September 19, 2017Assignee: TOKYO ELECTRON LIMITEDInventors: Takehisa Saito, Takenao Nemoto, Koji Yamagishi, Hiroshi Kaneko
-
Publication number: 20170069473Abstract: A method includes performing an etching process in a first process module, moving a workpiece formed by the etching process from the first process module to a second process module, and performing a film forming process on the workpiece in the second process module. In the performing the film forming process, an insulating film is formed on a first surface and a second surface of a laminated portion by plasma of a processing gas that contains hydrogen. In the performing the film forming process, an internal pressure of the second process module is 200 mTorr or more, and a hydrogen partial pressure of the second process module is 15 mTorr or less. The performing the etching process, the moving the workpiece, and the performing the film forming process are consistently performed in a state where oxygen is exhausted.Type: ApplicationFiled: September 2, 2016Publication date: March 9, 2017Applicant: TOKYO ELECTRON LIMITEDInventors: Yasuhiko SAITO, Takenao NEMOTO
-
Publication number: 20170009338Abstract: A plasma processing apparatus for alternately performing a first plasma processing step using first and second processing gases and a second plasma processing step using third and fourth processing gases. The apparatus includes: a processing container that has a dielectric window in a ceiling and removably accommodates a workpiece; an exhaust unit that evacuates the processing container; a processing gas supply unit that supplies the first, second, third, and fourth processing gases into the processing container; a first gas introduction unit including a top plate gas injection port, a dielectric window gas flow path, and a first external gas flow path; a second gas introduction unit including a sidewall gas injection port, a sidewall gas flow path, and a second external gas flow path; an electromagnetic wave supply unit that supplies electromagnetic waves into the plasma generating space; a bypass exhaust path; and an opening/closing valve.Type: ApplicationFiled: February 23, 2015Publication date: January 12, 2017Applicant: TOKYO ELECTRON LIMITEDInventors: Takehisa SAITO, Takenao NEMOTO, Koji YAMAGISHI, Hiroshi KANEKO
-
Patent number: 9543191Abstract: Provided are a semiconductor device and semiconductor-device manufacturing method that make it possible to improve the contact between an insulating film and a wiring member and the reliability thereof. This method for manufacturing a semiconductor device (100) includes a step in which a CF film (106) is formed on top of a semiconductor substrate (102), a step in which grooves (C) corresponding to a wiring pattern (P) are formed in the CF film (106), and a step in which a copper wiring member (114) is embedded in the grooves (C).Type: GrantFiled: February 21, 2013Date of Patent: January 10, 2017Assignees: ZEON CORPORATION, TOHOKU UNIVERSITYInventors: Takenao Nemoto, Takehisa Saito, Yugo Tomita, Hirokazu Matsumoto, Akihide Shirotori, Akinobu Teramoto, Xun Gu
-
Patent number: 9165771Abstract: A method and apparatus for doping a surface of a substrate with a dopant, with the dopant being for example phosphine or arsine. The doping is performed with a plasma formed primarily of an inert gas such as helium or argon, with a low concentration of the dopant. To provide conformal doping, preferably to form a monolayer of the dopant, the gas flow introduction location is switched during the doping process, with the gas mixture primarily introduced through a center top port in the process chamber during a first period of time followed by introduction of the gas mixture primarily through peripheral or edge injection ports for a second period of time, with the switching continuing in an alternating fashion as the plasma process.Type: GrantFiled: April 3, 2014Date of Patent: October 20, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Peter Ventzek, Takenao Nemoto, Hirokazu Ueda, Yuuki Kobayashi, Masahiro Horigome
-
Publication number: 20150255258Abstract: Provided is a plasma processing apparatus including: a rotary mounting table supported by a rotatory shaft arranged rotatably within a processing chamber and including multiple substrate placement units arranged side by side in a circumferential direction; a processing gas supplying section for supplying processing gas into the processing chamber; a plasma generating section wherein multiple microwave introducing mechanisms, each provided on the ceiling of the processing chamber so as to face the rotary mounting table and used for generating a plasma of the processing gas, are arranged in multiple rows spaced apart from each other from the inside of the movement path of the substrates when the rotary mounting table is rotated to the outside, each row of microwave introducing mechanisms being formed by arranging the microwave introducing mechanisms annularly side by side along the circumferential direction; and an exhaust unit that evacuates an inside of the processing chamber.Type: ApplicationFiled: June 18, 2013Publication date: September 10, 2015Applicant: TOKYO ELECTRON LIMITEDInventors: Toshihisa Nozawa, Masahide Iwasaki, Takenao Nemoto, Yasuo Kobayashi, Takehisa Saito
-
Publication number: 20150132929Abstract: Provided is a method for injecting a dopant into a substrate to be processed. A method in one embodiment of the present invention includes: (a) a step for preparing, in a processing container, a substrate to be processed; and (b) a step for injecting a dopant into the substrate by supplying a doping gas containing AsH3, an inert gas, and H2 gas to the inside of the processing container, and applying plasma excitation energy to the inside of the processing container. In the step of injecting the dopant, the ratio of hydrogen partial pressure to the gas total pressure in the processing container is set within the range of 0.0015-0.003.Type: ApplicationFiled: April 5, 2013Publication date: May 14, 2015Applicant: TOKYO ELECTRON LIMITEDInventors: Masahiro Horigome, Hirokazu Ueda, Masahiro Oka, Masahiro Yamazaki, Takenao Nemoto
-
Publication number: 20150110973Abstract: A plasma processing apparatus of the present disclosure includes a processing container configured to accommodate a wafer; a placing unit provided on a bottom surface of the processing container to place the wafer thereon; a first processing gas supply pipe provided in a central portion of a ceiling of the processing container to supply a first processing gas into the processing container; a second processing gas supply pipe provided in a side wall of the processing container to supply a second processing gas into the processing container; a rectifying gas supply pipe provided in the side wall of the processing container above the second processing gas supply pipe to supply a rectifying gas downward into the processing container; and a radial line slot antenna configured to radiate microwave into the processing container.Type: ApplicationFiled: October 20, 2014Publication date: April 23, 2015Applicant: TOKYO ELECTRON LIMITEDInventors: Takenao NEMOTO, Toshihisa NOZAWA
-
Publication number: 20150041983Abstract: Provided are a semiconductor device and semiconductor-device manufacturing method that make it possible to improve the contact between an insulating film and a wiring member and the reliability thereof. This method for manufacturing a semiconductor device (100) includes a step in which a CF film (106) is formed on top of a semiconductor substrate (102), a step in which grooves (C) corresponding to a wiring pattern (P) are formed in the CF film (106), and a step in which a copper wiring member (114) is embedded in the grooves (C).Type: ApplicationFiled: February 21, 2013Publication date: February 12, 2015Applicants: TOKYO ELECTRON LIMITED, TOHOKU UNIVERSITY, ZEON CORPORATIONInventors: Takenao Nemoto, Takehisa Saito, Yugo Tomita, Hirokazu Matsumoto, Akihide Shirotori, Akinobu Teramoto, Xun Gu
-
Publication number: 20140302666Abstract: A method and apparatus for doping a surface of a substrate with a dopant, with the dopant being for example phosphine or arsine. The doping is performed with a plasma formed primarily of an inert gas such as helium or argon, with a low concentration of the dopant. To provide conformal doping, preferably to form a monolayer of the dopant, the gas flow introduction location is switched during the doping process, with the gas mixture primarily introduced through a center top port in the process chamber during a first period of time followed by introduction of the gas mixture primarily through peripheral or edge injection ports for a second period of time, with the switching continuing in an alternating fashion as the plasma process.Type: ApplicationFiled: April 3, 2014Publication date: October 9, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Peter VENTZEK, Takenao NEMOTO, Hirokazu UEDA, Yuuki KOBAYASHI, Masahiro HORIGOME
-
Publication number: 20140225263Abstract: During the production of a semiconductor device having a Cu wiring line of a damascene structure, diffusion of fluorine from a CF film that serves as an interlayer insulating film is prevented in cases where a heat treatment is carried out, thereby suppressing increase in the leakage current. A semiconductor device of the present invention having a damascene wiring structure is provided with: an interlayer insulating film (2) that is formed of, for example, a fluorine-added carbon film; and a copper wiring line (4) that is embedded in the interlayer insulating film. A barrier metal layer (6) close to the copper wiring line and a fluorine barrier film (5) close to the interlayer insulating film are formed between the interlayer insulating film and the copper wiring line.Type: ApplicationFiled: September 6, 2012Publication date: August 14, 2014Applicants: TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITEDInventors: Takenao Nemoto, Akinobu Teramoto, Xun Gu
-
Publication number: 20130130513Abstract: The interlayer insulating layer forming method for forming an interlayer insulating layer of a semiconductor device via a plasma CVD method includes: carrying a substrate into a depressurized processing container; supplying a plasma generating gas to a first space spaced apart from the substrate; exciting the plasma generating gas in the first space; and supplying a raw material gas including a boron compound that includes at least a hydrogen group or hydrocarbon group, to a second space between the first space and the substrate. Also, a semiconductor device is interconnected in a multilayer through an interlayer insulating layer having an amorphous structure including boron, carbon, and nitrogen, wherein, in the interlayer insulating layer, a hydrocarbon group or an alkyl amino group is mixed in the amorphous structure comprising hexagonal boron nitride and cubic boron nitride.Type: ApplicationFiled: July 20, 2011Publication date: May 23, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Kotaro Miyatani, Takenao Nemoto, Takuya Kurotori, Yasuo Kobayashi, Toshihisa Nozawa
-
Publication number: 20120125376Abstract: A wet processing apparatus holds on a stage a substrate to be processed and carries out a wet treatment by rotating the stage. The substrate is held by the stage, with the center of the substrate being offset from the rotation center of the stage, using a Bernoulli chuck which causes an inert gas to flow to a back surface of the substrate, so that the substrate is eccentrically rotated along with the rotation of the stage. A first gas supply passage which is used for the Bernoulli chuck is provided at a rotation shaft portion in the stage and the stage is also provided with second gas supply passages which communicate with the first gas supply passage to thereby introduce the inert gas to the back surface of the substrate. The second gas supply passages are axisymmetric with respect to a central axis of the substrate.Type: ApplicationFiled: May 27, 2010Publication date: May 24, 2012Applicants: TOKYO ELECTRON LIMITED, TOHOKU UNIVERSITYInventors: Tadahiro Ohmi, Tetsuya Goto, Takaaki Matsuoka, Takenao Nemoto, Yoriyuki Murakawa, Kazuhiro Yoshikawa
-
Publication number: 20100240283Abstract: [Problem] To improve polishing efficiency while lowering shear force added to semiconductor wafers while increasing polishing speed, without damaging the wafer's processing surface or the membrane under it. [Solution Method] Pressing the revolving head or carrier 34 that holds fixed the semiconductor wafer 10 to the polishing pad or polishing cloth 30 attached to rotating polishing table 32 in this CMP device and while rotating carrier 34 and polishing table 32 respectively, and supplying liquid slurry to polishing pad 30 from nozzle 36, planarization by chemical processes and mechanical processes is carried out by removing membranes of the lower face of semiconductor wafer 10 (the processing surface). The chemical mechanical polishing process of the present invention in regard to the size of the relationship between the rotation rate of semiconductor wafer 10 fW and the number of rotations of polishing pad 30 fP has 3 fp<fW as its lower limit and 4 fp<fW<8 fp is ideal conditions.Type: ApplicationFiled: September 25, 2009Publication date: September 23, 2010Applicants: ARACA Incorporation, Tokyo Electron Limited, Tohoku UniversityInventors: Takenao Nemoto, Tadahiro Ohmi, Akinobu Teramoto, Xun Gu, Ara Philipossian, Yasa Sampurno
-
Publication number: 20100159804Abstract: A method of determining pattern evolution of a semiconductor wafer during chemical mechanical polishing prior to polishing end point by determining the periodic change in the variance and FT or FFT frequency spectra of shear force and change in variance and FT or FFT frequency spectra of COF, shear force and/or down force between the semiconductor wafer and the polishing pad.Type: ApplicationFiled: December 22, 2008Publication date: June 24, 2010Applicant: ARACA, Inc.Inventors: Yasa Sampurno, Ara Philipossian, Akinobu Teramoto, Takenao Nemoto
-
Publication number: 20090108452Abstract: A method of manufacturing a semiconductor device including a sputtering process for forming a barrier film mainly having tantalum or tantalum nitride on an interlayer insulator formed by sputtering using a xenon gas. The sputtering process may include a step of forming one barrier film mainly composed of tantalum nitride on a substrate by sputtering using a xenon gas by applying a RF bias, and a step for forming another barrier film mainly composed of tantalum on the first barrier film by sputtering using a xenon gas without applying the RF bias. The barrier film may be formed by changing the RF bias continuously, and forming the interlayer insulator side by applying the RF bias, and forming the wiring side without applying the RF bias.Type: ApplicationFiled: October 31, 2008Publication date: April 30, 2009Applicants: Tokyo Electron Limited, Tohoku UniversityInventors: Takenao Nemoto, Akinobu Teramoto, Tadahiro Ohmi
-
Patent number: 6992011Abstract: A cleaning method is provided using a cleaning gas mixture of hydrogen and inert gas, for example a mixture in which the hydrogen content is between 20 percent and 80 percent by volume, provided to the chamber of a semiconductor wafer processing apparatus and an ICP power source only to generate a high density plasma in the gas mixture without biasing the surface to be cleaned. In examples of the invention, Si and SiO2 contaminants or CFx contaminants are cleaned from a silicon contact prior to subsequent metal deposition. In another example of the invention, silicon residue is cleaned from internal chamber surfaces before oxide etching to recover the baseline oxide etch rate.Type: GrantFiled: January 15, 2003Date of Patent: January 31, 2006Assignee: Tokyo Electron LimitedInventors: Takenao Nemoto, Emmanuel Guidotti, Gert Leusink
-
Publication number: 20040137750Abstract: A cleaning method is provided using a cleaning gas mixture of hydrogen and inert gas, for example a mixture in which the hydrogen content is between 20 percent and 80 percent by volume, provided to the chamber of a semiconductor wafer processing apparatus and an ICP power source only to generate a high density plasma in the gas mixture without biasing the surface to be cleaned. In examples of the invention, Si and SiO2 contaminants or CFx contaminants are cleaned from a silicon contact prior to subsequent metal deposition. In another example of the invention, silicon residue is cleaned from internal chamber surfaces before oxide etching to recover the baseline oxide etch rate.Type: ApplicationFiled: January 15, 2003Publication date: July 15, 2004Applicant: Tokyo Electron LimitedInventors: Takenao Nemoto, Emmanuel Guidotti, Gert Leusink
-
Patent number: 5565380Abstract: A semiconductor device having an interconnecting line formed of aluminum containing a predetermined additive element, wherein a segregate layer of the additive element is formed along aluminum grain boundaries in the interconnecting line on the basis of a heat treatment after the formation of the interconnecting line.Type: GrantFiled: December 27, 1993Date of Patent: October 15, 1996Assignee: Kawasaki Steel CorporationInventors: Takenao Nemoto, Takeshi Nogami, Naoki Matsukawa