Abstract: In a prior art disk subsystem formed by duplicating a shared memory (SM) in a DRAM (first area) and a SRAM (second area) having a higher speed than the DRAM, the data stored in the SRAM cannot be switched collectively while maintaining access to the SM, so that the access performance was deteriorated. According to the present invention, when there is a change in setting of data stored in a second area (SRAM), a data corresponding to the setting after the change is stored from a first area (DRAM) of a slave surface side SM to the second area (SRAM), and the setting of data of the second area (SRAM) is changed. After changing the setting, the slave surface side SM is changed to a master surface side SM.

Abstract: The storage controller of the present invention is able to reduce the amount of purge message communication and increase the processing performance of the storage controller. Each microprocessor creates and saves a purge message every time control information in the shared memory is updated. After a series of update processes are complete, the saved purge messages are transmitted to each microprocessor. To the control information, attribute corresponding to its characteristics is established, and cache control and purge control are executed depending on the attribute.

Abstract: A storage apparatus that provides a dynamically extensible virtual volume for a host apparatus that accesses the virtual volume is characterized by including: a management unit setting part for setting a management unit, with which an area for storing data sent from the host apparatus is divided on a predetermined-area basis for management, for a pool area that provides a storage area to be assigned to the virtual volume; and a management unit resetting part for resetting the management unit set by the management unit setting part via analysis of the status of access from the host apparatus to the data at a predetermined time to make the management unit optimum for the status of access from the host apparatus to the data.

Abstract: The storage controller of the present invention is able to reduce the amount of purge message communication and increase the processing performance of the storage controller. Each microprocessor creates and saves a purge message every time control information in the shared memory is updated. After a series of update processes are complete, the saved purge messages are transmitted to each microprocessor. To the control information, attribute corresponding to its characteristics is established, and cache control and purge control are executed depending on the attribute.

Abstract: A storage controller facilitating extending storage capacity while suppressing investment related to storage capacity is provided. System configuration information, including content of a definition of a virtual volume having a storage capacity that is larger than a real storage capacity including the storage capacity of a storage device unit, and content of a definition of at least one of a real volume formed by dividing the real storage capacity, and a pool area, is stored. Based on the system configuration information, relevant data is written to or read from an address position in the storage device unit in response to a data input/output request from the host system designating an address in the real volume, and data is written to or read from the pool area in response to a data input/output request from the host system designating an address in the virtual volume other than the real volume.

Abstract: An object of the present invention is to provide a storage controller capable of facilitating extension of storage capacity while suppressing investment related to storage capacity.

Abstract: A storage apparatus that provides a dynamically extensible virtual volume for a host apparatus that accesses the virtual volume is characterized by including: a management unit setting part for setting a management unit, with which an area for storing data sent from the host apparatus is divided on a predetermined-area basis for management, for a pool area that provides a storage area to be assigned to the virtual volume; and a management unit resetting part for resetting the management unit set by the management unit setting part via analysis of the status of access from the host apparatus to the data at a predetermined time to make the management unit optimum for the status of access from the host apparatus to the data.

Abstract: In a shared bus connection scheme or an individual path connection scheme, a fault caused at a part of a system affects the same in its entirety. Also, these schemes do not permit the determination of fault locations. Adapters 11, 12 are connected to shared memories 21, 22 with a plurality of individual paths 31 through 38. An address locking unit (not shown) is arranged in each of the shared memories 21, 22 to perform address lock check on memory access operations from the adapters 11, 12. If an address to be accessed is in the locked state, the access is held in the lock wait state until the address is unlocked. The access is made when the address locking is cleared.

Abstract: An object of the present invention is to provide a storage controller capable of facilitating extension of storage capacity while suppressing investment related to storage capacity.

Abstract: A storage subsystem in which write data written in a first storage subsystem from a plurality of host computers is copied onto a second storage subsystem, thereby protecting the write data in a multiplex manner. Disclosed are a storage subsystem and its controlling method in which the first storage subsystem has a storage control unit which sets a first threshold for controlling for each of the host computers an occupancy ratio of the write data whose copy to the second storage subsystem is incomplete in a data buffer in the first storage subsystem, and has control logic for delaying the processing of a data write request from each of the host computers on the basis of the first threshold.

Abstract: In a shared bus connection scheme or an individual path connection scheme, a fault caused at a part of a system affects the same in its entirety. Also, these schemes do not permit the determination of fault locations. Adapters 11, 12 are connected to shared memories 21, 22 with a plurality of individual paths 31 through 38. An address locking unit (not shown) is arranged in each of the shared memories 21, 22 to perform address lock check on memory access operations from the adapters 11, 12. If an address to be accessed is in the locked state, the access is held in the lock wait state until the address is unlocked. The access is made when the address locking is cleared.

Abstract: A storage subsystem in which write data written in a first storage subsystem from a plurality of host computers is copied onto a second storage subsystem, thereby protecting the write data in a multiplex manner. Disclosed are a storage subsystem and its controlling method in which the first storage subsystem has a storage control unit which sets a first threshold for controlling for each of the host computers an occupancy ratio of the write data whose copy to the second storage subsystem is incomplete in a data buffer in the first storage subsystem, and has control logic for delaying the processing of a data write request from each of the host computers on the basis of the first threshold.

Abstract: A storage subsystem in which write data written in a first storage subsystem from a plurality of host computers is copied onto a second storage subsystem, thereby protecting the write data in a multiplex manner. Disclosed are a storage subsystem and its controlling method in which the first storage subsystem has a storage control unit which sets a first threshold for controlling for each of the host computers an occupancy ratio of the write data whose copy to the second storage subsystem is incomplete in a data buffer in the first storage subsystem, and has control logic for delaying the processing of a data write request from each of the host computers on the basis of the first threshold.

Abstract: A method of recording a large quantity of data by one code mark. Four bit indicating fields (2a, 2b, 2c, 2d) for denoting a binary number of four bits are provided on the surface of a card (1). One numerical value is recorded by indicating predetermined bit parts of the four bit indicating fields (2a-2d) with the same color, and plural kinds of colors are mixedly given to the four bit indicating fields (2a-2d).

Abstract: A wiring circuit substrate comprises first circuit element means one one side of the substrate connected to electrode lines of X-Y matrix electrodes, respectively, and second circuit element means in the symmetrical position of the first circuit element means on the other side of the substrate connected to the electrode lines of the X-Y matrix electrodes, respectively, wherein each of leads of the first and the second circuit element means is connected to the output and input lines of the X-Y matrix electrodes via through holes, respectively.The first circuit element comprises integrated transisitors for driving the X-Y matrix electrodes. The second circuit element comprises integrated diodes for protecting an overcurrent in the X-Y matrix electrodes.

Abstract: A photosensitive composition wherein setting is retarded in the presence of air is subjected to partial setting by directing radiating light through the side in contact with air, thus setting the opposite side which is not in contact with air, with setting then completed by directing radiating light to the unset part of the composition in the absence of air. The composition is extended on a metal surface, with the surface in contact with the metal being subjected to setting, thus providing excellent smoothness. After the unset part of the composition is stuck by pressure to another unset composition or another film, the films can be adhered with radiating light. When metal rolls are utilized for the metal surfaces, continuous manufacturing can be easily achieved.

Abstract: An article holder for use in a car door comprises an insertion portion to be inserted in the space between a door glass and an inside door, a lateral holding portion continuing from the insertion member fold at an outside bend line and having a reinforcing member for reinforcing the lateral holding portion, the lateral holding portion having further a support member which can be adjusted by selectively bending at any of the inside fold lines depending on the thickness of the inside door, a tab for fixedly positioning the support member, a longitudinal holding portion continuing from the lateral holding portion, a truncated disc member which is substantially in shape and extends between the lateral holding portion and the longitudinal holding portion, a lateral inside support member provided in the longitudinal holding portion and continuing from the truncated disc member.

Abstract: A MOS transistor is featured by providing mult-layered covering elements for covering a channel region of the semiconductor device. Each of the covering elements is interposed by an insulating layer. Preferably, the covering layers comprise first and second covering layers neither of which are connected to either of the drain electrode, the source electrode, or the gate electrode. A field plate layer, as a third covering layer, is disposed over the first and second covering layers.

Abstract: A sealing technique is disclosed by which the firing voltage of atmospheric discharge is increased by a pressurizing procedure such that the internal pressure of a sealing chamber is held at room temperature above half (0.5) of the atmospheric pressure even after the completion of sealing. Preferably, the pressurizing procedure is accomplished by a partial modification in the existing sealing facilities (for example, belt furnaces and low temperature furnaces). In another aspect of the invention, the method for sealing a semiconductor device minimizes water in the chamber after sealing by suppressing water expelled from glass frit during sealing or allowing the glass frit to absorb the water expelled therefrom. In other words, sealing is performed first under nitrogen gas atmosphere and then under oxygen gas atmosphere.

Abstract: Formation of well-regions of a conductivity type opposite to that of a substrate is achieved in such a manner to determine a first threshold voltage level. Ion implantation is effected on desirably selected gates in the respective channels formed on the substrate and the well-regions. Two channels on the ion implanted substrate and on the well-region in which the ion implantation is not effected, are coupled to form a complementary-MOS transistor pair having a first threshold voltage level. The channels on the substrate in which the ion implantation is not effected and on the ion implanted well-region are coupled to form another complementary-MOS transistor pair having a second threshold voltage level.