Abstract: Provided is a transmission control apparatus that determine a first phase difference for a phase difference between an electric wave output by a first antenna and an electric wave output by a second antenna, and for a phase difference between an electric wave output by a third antenna and an electric wave output by a fourth antenna, based on a determined polarization characteristic; determines a second phase difference for a phase difference between the electric wave output by the first antenna and the electric wave output by the third antenna and for a phase difference between the electric wave output by the second antenna and the electric wave output by the fourth antenna, based on the determined beam direction; and controls phases of the electric waves output by the first to fourth antennas, according to the first and second phase differences.

Abstract: Provided is a transmission control apparatus that, at a first transmission timing, causes a first symbol to be transmitted from a first antenna, causes the first symbol having the same phase as the first symbol transmitted from the first antenna to be transmitted from a second antenna that is orthogonal to the first antenna and has a path to a mobile terminal that is the same as a path between the first antenna and the mobile terminal, causes a second symbol to be transmitted from a third antenna arranged parallel to the first antenna, and causes the second symbol having the inverse phase of the second symbol transmitted from the third antenna to be transmitted from a fourth antenna that is orthogonal to the third antenna and has a path to the mobile terminal that is the same as a path between the third antenna and the mobile terminal.

Abstract: Provided is a transmission control apparatus that, at a first transmission timing, causes a first symbol to be transmitted from a first antenna, causes the first symbol having the same phase as the first symbol transmitted from the first antenna to be transmitted from a second antenna that is orthogonal to the first antenna and has a path to a mobile terminal that is the same as a path between the first antenna and the mobile terminal, causes a second symbol to be transmitted from a third antenna arranged parallel to the first antenna, and causes the second symbol having the inverse phase of the second symbol transmitted from the third antenna to be transmitted from a fourth antenna that is orthogonal to the third antenna and has a path to the mobile terminal that is the same as a path between the third antenna and the mobile terminal.

Abstract: Provided is a transmission control apparatus that determine a first phase difference for a phase difference between an electric wave output by a first antenna and an electric wave output by a second antenna, and for a phase difference between an electric wave output by a third antenna and an electric wave output by a fourth antenna, based on a determined polarization characteristic; determines a second phase difference for a phase difference between the electric wave output by the first antenna and the electric wave output by the third antenna and for a phase difference between the electric wave output by the second antenna and the electric wave output by the fourth antenna, based on the determined beam direction; and controls phases of the electric waves output by the first to fourth antennas, according to the first and second phase differences.

Abstract: A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately.

Abstract: There are provided an IP telephone system and method for establishing a connection to the IP network 4 via a public line network and performing talking by transmitting/receiving IP packet data into which audio data has been converted. In a location server 3 arranged on a PSTN 5 or the IP network 4, a public line telephone number and an IP telephone number which are attached to the line connected to a telephone terminal 1a and a terminal identifier identifying the telephone terminal 1a are registered while correlating them to each other. When an IVR 8 is called, the public line telephone number, the IP telephone number of the telephone terminal 1a and/or the terminal identifier is acquired from the telephone terminal 1a and the registration content in the location server 3 is modified via a registrar system 7.

Abstract: A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately.

Abstract: An IP terminal 1 at a transmitting end has a copying unit 111 for copying packet data to be transmitted; an address setting unit 112 for adding unique address information to the respective copied packet data having the same contents; and a transmitting unit 113 for outputting, based on the address information, the copied packet data to different paths 1, 2 on an IP network 3. An IP terminal 5 has a selecting unit 523 for selecting and acquiring the first arriving packet data of the copied packet data having the same contents. In this way, for a data communication in a communication network such as Internet, a plurality of communication paths are used in a packet network, thereby reducing packet jitter and loss at the receiving end and providing a real time service having substantially the same quality as in a line exchanging network.

Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

Abstract: The present invention relates to a booster circuit of a non-volatile memory requiring a plus or minus high voltage equal to or higher than a power-supply voltage. The present invention can generate a high voltage of approximately 12 V even at a low power-supply voltage equal to or lower than 3 V and generate not only a plus high voltage but also a minus high voltage by the same circuit. Also, by combining a body-controlled type parallel charge pump, which is a booster circuit according to the present invention, with a serial-type charge pump, two types of high voltages can be efficiently generated and a reduction in chip areas can be achieved.

Abstract: Information services are provided via an over-the-air television broadcasting system that is segmented into a plurality of cells. Each cell includes one or more transmitting facilities for transmitting service information and mapping information. The mapping information includes adjacent cell information enabling mobile receiver units to transition between cells in order to continue receipt of service information without requiring communication from the receiver unit to the service provider. The transmitting facilities of adjacent cells may operate on the same television channel and/or on different television channels, typically chosen from a frequency set allocated to a given service provider. The service information may include different content in different cells, such as local content specific to each cell. The service information may be provided from one or more content servers in communication with the transmitting facilities.

Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

Abstract: A non-volatile semiconductor memory EEPROM is usually deteriorated depending on the number of times of program and erase operations and application years thereof. A read operation rate of the EEPROM is generally specified to the operation rate considering deterioration of memory and even in the case where the number of times of program and erase operations is rather small and application years are also rather small, the read operation has been conducted at the read operation rate specified considering deterioration of memory. Moreover, when deterioration of memory is advanced exceeding the specified deterioration, the read operation is now disabled in the worst case. In order to overcome such problem, the reference memories are allocated for every erase and program unit block in the EEPROM memory array, the reference memories are also programmed and erased whenever the memories in the block are erased and programmed and the read timing of memory is generated from the read timing of these reference memories.

Abstract: The present invention relates to a booster circuit of a non-volatile memory requiring a plus or minus high voltage equal to or higher than a power-supply voltage. The present invention can generate a high voltage of approximately 12 V even at a low power-supply voltage equal to or lower than 3 V and generate not only a plus high voltage but also a minus high voltage by the same circuit. Also, by combining a body-controlled type parallel charge pump, which is a booster circuit according to the present invention, with a serial-type charge pump, two types of high voltages can be efficiently generated and a reduction in chip areas can be achieved.

Abstract: Power wastefully consumed in a memory in standby state is reduced without lowering the speed of operation of reading data out of the memory. A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

Abstract: A non-volatile semiconductor memory EEPROM is usually deteriorated depending on the number of times of program and erase operations and application years thereof. A read operation rate of the EEPROM is generally specified to the operation rate considering deterioration of memory and even in the case where the number of times of program and erase operations is rather small and application years are also rather small, the read operation has been conducted at the read operation rate specified considering deterioration of memory. Moreover, when deterioration of memory is advanced exceeding the specified deterioration, the read operation is now disabled in the worst case. In order to overcome such problem, the reference memories are allocated for every erase and program unit block in the EEPROM memory array, the reference memories are also programmed and erased whenever the memories in the block are erased and programmed and the read timing of memory is generated from the read timing of these reference memories.

Abstract: When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.