Abstract: The present invention relates to a circuit controlling terminal equipment identifiers identifying said terminal equipment in a communicating apparatus wherein a number of the above-mentioned terminal equipment are connected to a network, and makes it possible to reduce the amount of hardware make the operation faster and facilitate the control of TEI assignment by using the address of a memory storing binary data as the TEI value.

Abstract: A bit length corresponding to a delay time of required data is preset in a bit length setting circuit (15). A write timing signal from an external control circuit (6) is applied to a write address decoder (3) and a read timing signal generating circuit (2). Input data is written into memory cells in a memory device (5) addressed by the write address decoder (3) operating in response to the write timing signal. On the other hand, a read timing signal generating circuit (2) generates a read timing signal delayed from the write timing signal by a delay time corresponding to a bit length signal in response to the bit length signal from the bit length setting circuit (15) and the write timing signal from outside. The read address decoder (4) sequentially addresses memory cells containing input data which have been written, reads written data and then outputs output data. Applications of the circuit include frame synchronization, variable delay and storage of picture data in a video communications system.

Abstract: This invention relates to a standard cell system large scale integrated circuit which comprises arraying a plurality of standard cells that are equally dimensioned in at least one direction and interconnection said standard cells so as to constitute a logic device, whereby the improvement is characterized in that wiring carrying a heavy load and being connected at many places on the surface of the chip is located within each of the standard cells, furthermore said wiring carrying a heavy load and being connected at many places on the surface of the chip is a clock line, and said clock line is located between a power line and a grounding conductor provided within each standard cell.

Abstract: The clock signal generator for generating non-overlapping polyphase clock pulses having no overlapping period of time where the clock pulses have a high level at the same time, comprises a clock signal generation control means provided for each of the polyphase clock pulses so that a clock signal on a signal path where the largest delay is caused among at the signal paths of one phase is used to prevent clock signal generation in the other phases.

Abstract: In a periodic signal generator circuit, logical threshold values of an inverter for inverting an output signal of a first logical gate circuit (1) and inputting the same to a second logical gate circuit (2) and an inverter (40) for inverting an output signal of the second logical gate circuit (2) and inputting the same to the first logical gate circuit are set low, so that the time when an output signal of one of the logical gate circuits (1, 2) is inverted by inverting an output signal of the other logical gate circuit is delayed. Thus, the periodic signal generator circuit generates a so-called two-phase non-overlapped clock signal.

Abstract: A bidirectional elastic store circuit comprises an elastic store portion (1) having a node (A) for writing data and a node (B) for reading out data, an input terminal (8) and an output terminal (9) for data communication in a first direction, an input terminal (10) and an output terminal (11) for data communication in a second direction opposite to the first direction, a group of logical circuits (13) for selecting either the input terminals (8, 10) and a group of logical circuits (14) for selecting either the output terminals (9, 11). At the time of data communication in the first direction, a switching signal EN1/EN2 applied from an input terminal (12) becomes high, so that the input terminal (8) and the output terminal (9) are coupled to the elastic store portion (1) through the nodes (A) and (B), respectively.

Abstract: A comparator circuit for comparing an input signal Ein with a reference signal Vref. The comparator circuit includes an input circuit 1, a capacitor 4, first and second supply circuits 15,16, a voltage-stabilizing circuit 6, an output circuit 7 and control means .phi., .phi.. The input circuit selectively supplies either the input signal, or the reference signal to node 1N. The first supply circuit 15 supplies potential VDD to node 3N when the potential at node 2N is above a first voltage potential V1, and the second supply circuit supplies potential VDD to node 4N when the potential at the second node is above a second voltage potential V2. The voltage-stabilizing circuit 6 selectively connects the output terminal to a supply terminal, or a ground terminal. The output circuit includes an inverter circuit 2 and a switching circuit 3.

Abstract: An address comparator compares a write address value and a read address value for designating addresses in an elastic store circuit. More specifically, the count output of a write address counter (20) for counting a write clock signal is decoded by a write address decoder (30) and the count output of a read address counter (50) for counting a read clock signal is decoded by a read address decoder (40). The respective decoded outputs are classified into a plurality of groups so as to be supplied to a logical circuit group (10). The logical circuit group (10) provides a signal for giving an alarm when the output address value of the write address counter (20) is applied in a predetermined number of address groups including as the center the address group to which the output address value of the read address counter (50) belongs.