Patents by Inventor Takesada Akiba
Takesada Akiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050035403Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: September 20, 2004Publication date: February 17, 2005Applicants: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William McKee, Jeffrey Koelling, Troy Herndon
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Publication number: 20040263446Abstract: By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained.Type: ApplicationFiled: April 23, 2004Publication date: December 30, 2004Applicant: Renesas Technology Corp.Inventors: Yasushi Kawase, Takesada Akiba, Kazuya Endo, Goro Sakamaki
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Patent number: 6831317Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: December 10, 2002Date of Patent: December 14, 2004Assignee: Hitachi, Ltd.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6815742Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: December 5, 2003Date of Patent: November 9, 2004Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Publication number: 20040217776Abstract: A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.Type: ApplicationFiled: June 3, 2004Publication date: November 4, 2004Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
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Publication number: 20040129974Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: December 5, 2003Publication date: July 8, 2004Applicants: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6747509Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.Type: GrantFiled: January 15, 2002Date of Patent: June 8, 2004Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
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Publication number: 20030067018Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: December 10, 2002Publication date: April 10, 2003Applicant: Hitachi, Ltd.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Publication number: 20030043680Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.Type: ApplicationFiled: July 9, 2002Publication date: March 6, 2003Applicant: Hitachi, Ltd.Inventors: Takesada Akiba, Shigeki Ueda, Toshikazu Tachibana, Masashi Horiguchi
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Patent number: 6512257Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: April 11, 2002Date of Patent: January 28, 2003Assignees: Hitachi, Inc., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Publication number: 20020140015Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size ofthe circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: April 11, 2002Publication date: October 3, 2002Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6396088Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: July 19, 2001Date of Patent: May 28, 2002Assignee: Hitachi, Ltd.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Publication number: 20020057129Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.Type: ApplicationFiled: January 15, 2002Publication date: May 16, 2002Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
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Patent number: 6339358Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.Type: GrantFiled: February 28, 2000Date of Patent: January 15, 2002Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
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Publication number: 20020000583Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: July 19, 2001Publication date: January 3, 2002Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6288925Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: February 1, 2000Date of Patent: September 11, 2001Assignees: Hitachi, LTD, Texas Instruments, Inc.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6115279Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: October 10, 1996Date of Patent: September 5, 2000Assignee: Hitachi Ltd.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6107869Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.Type: GrantFiled: June 11, 1998Date of Patent: August 22, 2000Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
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Patent number: 6069813Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: June 11, 1999Date of Patent: May 30, 2000Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6028800Abstract: An apparatus and method for a logic circuit that advantageously adapts to different operating voltages. In a preferred embodiment, a logic circuit of the present invention is implemented to drive a large capacitive load and includes a first driver, comprising a set of small, low-current drive transistors, a second driver, comprising a set of large, high-speed transistors, and an additional transistor connected between the two drivers. The additional transistor can be selectively enabled to speed up the operation of the logic circuit, and disabled to reduce the peak current of the logic circuit. The additional transistor is enabled by a voltage detection signal, which is active when the operating voltage of the chip is at a low level and inactive when the operating voltage of the chip is at a high level.Type: GrantFiled: October 15, 1996Date of Patent: February 22, 2000Assignee: Hitachi Ltd, of JapanInventors: Takesada Akiba, Goro Kitsukawa, Hiroshi Otori, Masayuki Nakamura, Hideo Sunami, Adin Hyslop