Abstract: A router comprising a priority level distinguishing means for distinguishing the priority level of a packet by referring to the information contained in the header of the packet, a routing table where an output path comprising one or more output lines can be mapped to each level of priority, an output path determining unit that searches the routing table and determines an output path to be used for sending out packets, and a preferential delivery controller that executes delivery control in accordance with the priority level for each output line corresponding to the output path. In response to a fault state in a preferred output line, the router can reroute high priority packets over an alternative output line while maintaining priority. The router may also calculate a distribution ratio to determine the optimal load for each output line for a given packet priority.

Abstract: A packet communication system of the present invention has first mode, second mode and third mode to apply to input packets. The first mode is a mode that decides priority of the packet by at least one of the address information and the application information, the second mode is a mode that decides priority of the packet by the DS value, the third mode is a mode that decides rewrite the DS value by at least one of the address information and the application information. A control unit of the packet communication system switches a mode to apply an input packet of the first mode, the second mode and the third mode based on the packet header information of the input packet.

Abstract: A packet communication system of the present invention has first mode, second mode and third mode to apply to input packets. The first mode is a mode that decides priority of the packet by at least one of the address information and the application information, the second mode is a mode that decides priority of the packet by the DS value, the third mode is a mode that decides rewrite the DS value by at least one of the address information and the application information. A control unit of the packet communication system switches a mode to apply an input packet of the first mode, the second mode and the third mode based on the packet header information of the input packet.

Abstract: When a packet arrives at a shaping unit 500, a discard control unit 510 judges whether to “store” or “discard” the arrived packet. Packets judged to be “stored” are stored into a packet storage FIFO buffer 520 and sent out within a transmission bandwidth greater than the total sum of user-by-user minimum bandwidths. A bandwidth check unit 600 checks bandwidth per user and judges packets that fall within the bandwidth to be high priority packets and packets that fall outside the bandwidth to be low priority packets. If a large quantity of packets are stored into the packet storage FIFO buffer 520, the discard control unit 510 determines that low priority packets are exclusively “discarded,” thus securing high priority packets from being discarded. Thereby, the shaping unit 500 ensures proper packet transmission within user-specific minimum bandwidth.

Abstract: In a device that interworks a VLAN network and an MPLS network, a VLAN ID is associated with an MPLS label. In a device that performs interworking from a VLAN network to an MPLS network, an output MPLS label is determined from a pair of a VLAN ID and the information in the layer 3 or layer 4 header of a packet. The output MPLS label is assigned an independent value for each VLAN. In a device that performs interworking from the MPLS network to another VLAN network, the input MPLS label is associated with a VLAN ID.

Abstract: An ATM switch having a packet level discard function includes an upstream congestion detection circuit for detecting a congestion state of an ATM switch provided in the upstream and a packet level discard control table for holding at every connection a packet level discard priority indicating whether the ATM switch provided in the upstream has the packet level discard function or not, and wherein cells transmitted via an ATM switch not having a packet level discard function or an ATM switch which is not in the congestion state are packet-level-discarded with a priority to other cells. Thus, it is possible to improve a goodput of the ATM network in which ATM switches having a packet level discard function and ATM switches not having a packet level discard function are provided in a mixed state.

Abstract: A packet switch for setting a connection between a transmission source of a packet and a reception destination thereof so as to perform communication. The invention includes a packet buffer which includes at least one input port and a plurality of output ports. An input packet from the input port is delivered to at least one output port in accordance with address information of the input packet and connection information having been set in the packet switch at the time of setting the connection between the transmission source and the reception destination. A bandwidth management packet for giving notice of a congested state of the packet switch is transferred on the connection.

Abstract: Cells are discarded in conformity with the order of priority when congestion occurs by discarding cells of a traffic class without any special contract for a transfer rate at the time of setting up a connection. A node stores priority information concerning cell discard corresponding to a connection identifier and controls the cell discard in accordance with the discard condition determined by the accumulated number of cells for each connection in the node and cell priority.

Abstract: For setting up a connection belonging to a particular traffic class which does not make a bandwidth reservation, information indicative of a priority related to cell discard declared by a source unit is stored in any node in an ATM network corresponding to an identifier of the connection, such that the node selectively performs discard processing on cells belonging to the particular traffic class, when congestion occurs on the connection, in conformity with a predetermined discard condition determined by a relationship between the status of the congestion and the priority. Accordingly, traffic can be protected for connections having higher priorities even if they do not make a bandwidth reservation.

Abstract: A data communication system for a computer system in which a plurality of computers are mutually connected includes: a plurality of computers each having an area to store a command to execute a data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the plurality of computers; and a transmission permitting component, connected between the switch circuit and one of the plurality of computers, for outputting a signal to permit the data transmission from such one computer to such another computer; a communication component for transmitting the data received from such one computer by outputting the transmission permission signal from the transmission permitting component to such another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from such one computer to such another computer; and a communication control component to abandon the data that is subsequently recei

Abstract: A data communication system for a computer system in which computers are mutually connected includes: each computer having an area to store a command to execute data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the computers; and a transmission permitting component, connected between the switch circuit and one of the computers, for outputting a signal to permit the data transmission from one computer to another computer; a communication component for transmitting the data received from one computer by outputting the transmission permission signal from the transmission permitting component to another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from one computer to another computer; and a communication control component to abandon the data that is subsequently received from one computer by outputting the transmission permission signal in accordance with

Abstract: A large-scaled interconnection switch in which a plurality of data processors are interconnected to perform data transfer between one another. The switch includes communication controllers, one provided for each of the plurality of data processors, divided into groups, for controlling communication between the data processors. Each group of communication controllers is connected by a signal line having a multiple bit width. A switch arbiter for arbitrates switch setting requests for interconnection of the data processors from the communication controllers to output a switch setting control signal. The switch also includes bit slice switches having a predetermined bit division count and to which respective/output signal lines are connected which bit-divide input/output signals of the communication controllers.

Abstract: The present invention relates to a network communication method and a network system that enables received data to be transferred directly to the user data region, thereby eliminating the need to perform data copy operations. In the present invention, packets are each provided with received region assignment information (port ID) for showing the region in which the packet is to be received and/or division information for dividing the packet. The region which is to receive data contained in the packet is determined from a port table and conversion tables, and the packet data is transferred to the region directly.

Abstract: A data processing system is provided which includes a plurality of subsystems each including at least one instruction processor, at least one input/output device and at least one main storage device connected by local bus. The subsystems are connected to one another through bus extenders and inter-subsystem transfer lines. Each of the main storage devices is assigned for a partial address space as a part of the system address space. When an instruction processor or an input/output processor on each of the subsystems makes access to a main storage device, the operation of the system is as follows. If the address of access is in the address space limit of a main storage device on an inner subsystem, access to the main storage device on the inner subsystem is made.

Abstract: A cache memory contained in a processor features a high efficiency in spite of its small capacity.In the cache memory control circuit, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory.By assigning the particular region for the data that is to be used repeatedly, it is possible to provide a cache memory having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.