Patents by Inventor Takeshi Aoki

Takeshi Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220402270
    Abstract: A printer includes a line head, a transport unit, a head moving unit, a maintenance unit, a lid unit, and a rotation mechanism portion. The head moving unit moves the line head to a retreat position and a recording position along a B direction. The maintenance unit includes a cap portion configured to cover the nozzles, is formed with an opening, and is movable in a transport direction of a medium. A lid unit is rotatable about a rotation axis, and closes the opening in a closed posture. When the head moving unit moves the line head from the recording position to the retreat position, the rotation mechanism portion rotates the lid unit so that a posture of the lid unit becomes the closed posture.
    Type: Application
    Filed: August 23, 2022
    Publication date: December 22, 2022
    Inventors: Masaki SHIMOMURA, Takuto TANAKA, Takeshi AOKI, Yusaku AMANO
  • Patent number: 11516418
    Abstract: A solid-state imaging apparatus according to an embodiment of the present disclosure includes a photoelectric transducer, a transfer transistor, a floating diffusion, a reset transistor, an amplifier transistor, and a selection transistor. The reset transistor includes a gate insulating film formed thinner than the gate insulating film of the transfer transistor.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 29, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takeshi Aoki
  • Publication number: 20220374203
    Abstract: A semiconductor device that inhibits signal delay and can perform parallel product-sum operations is provided. The semiconductor device includes first to fourth registers, an adder, a multiplier, a selector, and a first memory unit. An output terminal of the first register is electrically connected to an input terminal of the second register, and an output terminal of the second register is electrically connected to a first input terminal of the multiplier. An output terminal of the multiplier is electrically connected to a first input terminal of the adder, and an output terminal of the adder is electrically connected to an input terminal of the third register. An output terminal of the third register is electrically connected to a first input terminal of the selector, and an output terminal of the selector is electrically connected to an input terminal of the fourth register, and the first memory unit is electrically connected to a second input terminal of the multiplier.
    Type: Application
    Filed: October 15, 2020
    Publication date: November 24, 2022
    Inventors: Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takeshi AOKI, Takuro KANEMURA
  • Patent number: 11485140
    Abstract: A printer includes a line head, a transport unit, a head moving unit, a cap unit, and a wiper unit. The head moving unit moves the line head to a recording position and a retracted position along a B direction. The cap unit is configured to move back and forth in an A direction between the line head and the transport unit. The wiper unit is configured to move back and forth in a Y direction intersecting both the B direction and the A direction between the line head and the transport unit. At least a portion of a first movement area in which the cap unit moves and at least a portion of a second movement area in which the wiper unit moves are disposed at an identical position in the B direction.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: November 1, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Aoki, Yusaku Amano
  • Publication number: 20220343954
    Abstract: A semiconductor device in which energy required for data transfer between an arithmetic device and a memory is reduced is provided. The semiconductor device includes a peripheral circuit and a memory cell array. The peripheral circuit has a function of a driver circuit and a control circuit for the memory cell array, and an arithmetic function. The peripheral circuit includes a sense amplifier circuit and an arithmetic circuit, and the memory cell array includes a memory cell and a bit line. The sense amplifier circuit has a function of determining whether the bit line is at a high level or a low level, and outputs the result to the arithmetic circuit. The arithmetic circuit has a function of performing a product-sum operation, the result of which is output from the semiconductor device.
    Type: Application
    Filed: September 8, 2020
    Publication date: October 27, 2022
    Inventors: Takeshi AOKI, Munehiro KOZUMA, Masashi FUJITA, Takahiko ISHIZU
  • Publication number: 20220315373
    Abstract: A main body frame of a multifunction machine has first and second frames of which surfaces parallel to a Z-axis face each other. A recording head is disposed between the first and the second frames and fixed to the main body frame. An ejection tray is fixed to the main body frame on a +Z direction with respect to the recording head. A scanner is fixed to the main body frame on the +Z direction with respect to the ejection tray and forms an ejection space with the ejection tray. The recording head performs recording on a medium which is being transported toward a first direction, which is an in-plane direction of the first frame. The ejection tray is configured to be removed toward a second direction, which is the in-plane direction of the first frame, in a state where the scanner is fixed to the main body frame.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 6, 2022
    Inventors: Koji Oda, Koji SHIMIZU, Yuji Misawa, Takeshi Aoki
  • Publication number: 20220320830
    Abstract: A surface-emitting laser includes a lower DBR layer, a cavity layer, and an upper DBR layer that are stacked in this order on top of a substrate, wherein the lower DBR layer has a first DBR layer, a contact layer, and a second DBR layer that are stacked in this order on top of the substrate, wherein the first DBR layer and the second DBR layer each include a plurality of first layers and a plurality of second layers that are alternately stacked, wherein the first layers and the second layers are each a semiconductor layer including aluminum, wherein a composition ratio of the aluminum of each first layer is lower than a composition ratio of the aluminum of each second layer, and wherein the second DBR layer includes 12 or more and 20 or fewer pairs of the first layers and the second layers.
    Type: Application
    Filed: March 31, 2020
    Publication date: October 6, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takeshi AOKI, Susumu YOSHIMOTO
  • Patent number: 11458733
    Abstract: A printer includes a line head, a transport unit, a head moving unit, a maintenance unit, a lid unit, and a rotation mechanism portion. The head moving unit moves the line head to a retreat position and a recording position along a B direction. The maintenance unit includes a cap portion configured to cover the nozzles, is formed with an opening, and is movable in a transport direction of a medium. A lid unit is rotatable about a rotation axis, and closes the opening in a closed posture. When the head moving unit moves the line head from the recording position to the retreat position, the rotation mechanism portion rotates the lid unit so that a posture of the lid unit becomes the closed posture.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: October 4, 2022
    Assignee: Seiko Epson Corporation
    Inventors: Masaki Shimomura, Takuto Tanaka, Yusaku Amano, Takeshi Aoki
  • Patent number: 11453229
    Abstract: A recording apparatus includes: an apparatus body that includes a recorder that performs recording on a medium; an opening-and-closing member that is able to be opened away from and closed toward the apparatus body; a unit module that is detachably attached to an attachment portion configured to become exposed by opening the opening-and-closing member, and constitutes a part of a first medium transportation path when attached to the attachment portion; a second medium transportation path that is provided above the first medium transportation path; and a path forming member that is located above the attachment portion and forms a part of the second medium transportation path; wherein the path forming member is retracted from the second medium transportation path and advances onto the opening-and-closing trajectory of the opening-and-closing member when the unit module is detached from the attachment portion.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 27, 2022
    Assignee: Seiko Epson Corporation
    Inventor: Takeshi Aoki
  • Publication number: 20220294402
    Abstract: A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. In a semiconductor device, one of a source and a drain of a first transistor is electrically connected to one of a source and a drain of a second transistor and one of a source and a drain of a third transistor; the other of the source and the drain of the third transistor is electrically connected to a first output terminal; and the other of the source and the drain of the second transistor is electrically connected to a second output terminal.
    Type: Application
    Filed: August 11, 2020
    Publication date: September 15, 2022
    Inventors: Kei TAKAHASHI, Takeshi AOKI, Munehiro KOZUMA, Takayuki IKEDA
  • Publication number: 20220276834
    Abstract: A semiconductor device which can efficiently perform reading of a weight coefficient and a product-sum operation is provided. The semiconductor device includes a product-sum operation circuit and a memory device. The product-sum operation circuit is formed using transistors formed on a semiconductor substrate, and a memory cell of the memory device is formed using an OS transistor provided to be stacked above the semiconductor substrate. The semiconductor device includes a plurality of product-sum operation units where the product-sum operation circuit and the memory cell of the memory device are electrically connected to each other. In each of the product-sum operation units, a weight coefficient stored in the memory cell can be read and a product-sum operation can be performed.
    Type: Application
    Filed: June 29, 2020
    Publication date: September 1, 2022
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takuro KANEMURA
  • Publication number: 20220276839
    Abstract: A semiconductor device includes a CPU and an accelerator that includes a first memory circuit, a driver circuit, and a product-sum operation circuit. The first memory circuit includes a first data retention portion, a second data retention portion, and a data reading portion. The first data retention portion, the second data retention portion, and the data reading portion each include a first transistor. The first transistor contains a metal oxide in a channel formation region. First data stored in the first data retention portion and second data stored in the second data retention portion are each weight data input to the product-sum operation circuit. The product-sum operation circuit has a function of performing product-sum operation of the weight data and input data input through the driver circuit. The product-sum operation circuit and the driver circuit each include a second transistor. The second transistor contains silicon in a channel formation region.
    Type: Application
    Filed: September 18, 2020
    Publication date: September 1, 2022
    Inventors: Takahiko ISHIZU, Takeshi AOKI, Kazuma FURUTANI, Takayuki IKEDA, Shunpei YAMAZAKI
  • Publication number: 20220276838
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.
    Type: Application
    Filed: April 8, 2022
    Publication date: September 1, 2022
    Inventors: Munehiro KOZUMA, Takeshi AOKI, Seiichi YONEDA, Yoshiyuki KUROKAWA
  • Patent number: 11430820
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: August 30, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Publication number: 20220262953
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.
    Type: Application
    Filed: July 27, 2020
    Publication date: August 18, 2022
    Inventors: Munehiro KOZUMA, Takahiko ISHIZU, Takeshi AOKI, Masashi FUJITA, Kazuma FURUTANI, Kousuke SASAKI
  • Publication number: 20220254401
    Abstract: A semiconductor device resistant to a high temperature with low power consumption is provided. The semiconductor device includes a first and a second circuit, a first and a second cell, and a first and a second wiring. The first cell includes a first transistor, and the second cell includes a second transistor. The first and the second transistor operate in a subthreshold region. The first cell is electrically connected to the first circuit through the first wiring, the first cell is electrically connected to the second circuit through the second wiring, and the second cell is electrically connected to the second circuit through the second wiring. The first cell sets a current flowing through the first transistor to a first current and the second cell sets a current flowing through the second transistor to a second current. At this time, a potential corresponding to the second current is input from the second wiring to the first cell.
    Type: Application
    Filed: June 8, 2020
    Publication date: August 11, 2022
    Inventors: Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takeshi AOKI
  • Publication number: 20220224079
    Abstract: A vertical-cavity surface-emitting laser includes a substrate having a main surface, a first lower distributed Bragg reflector that extends to an edge of the main surface, a III-V compound semiconductor layer disposed on the first lower distributed Bragg reflector, a second lower distributed Bragg reflector disposed on the III-V compound semiconductor layer, an active layer disposed above the second lower distributed Bragg reflector and an upper distributed Bragg reflector disposed on the active layer. The first lower distributed Bragg reflector includes a first layer and a second layer that are alternately arranged. The upper distributed Bragg reflector includes a third layer and a fourth layer that are alternately arranged. The III-V compound semiconductor layer is free of aluminum or has an aluminum composition less than an aluminum composition of the third layer. The first layer has an aluminum composition greater than the aluminum composition of the third layer.
    Type: Application
    Filed: December 1, 2021
    Publication date: July 14, 2022
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Takeshi AOKI
  • Publication number: 20220208245
    Abstract: A semiconductor device with reduced power consumption is provided. The semiconductor device includes a transmitter unit, a receiver unit, a bias-outputting unit, and a controller unit. The bias-outputting unit has a plurality of memory units. The plurality of memory units each retains information to determine transmission power. The receiver unit receives a request signal transmitted from a base station and supplies it to the controller unit. The controller unit selects one of the plurality of memory units according to the request signal. The memory unit has an OS transistor and retains information when power supply is stopped.
    Type: Application
    Filed: April 13, 2020
    Publication date: June 30, 2022
    Inventors: Munehiro KOZUMA, Takayuki IKEDA, Kei TAKAHASHI, Takeshi AOKI
  • Publication number: 20220190398
    Abstract: A semiconductor device with reduced power consumption is provided. With three transistors, potentials of two nodes are switched and a voltage is detected. One of a source and a drain of a first transistor is electrically connected to a first terminal. The other of the source and the drain of the first transistor is electrically connected to a non-inverting input of a comparator through a first node. One of a source and a drain of a second transistor is electrically connected to a second terminal. The other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of a third transistor through a second node. The other of the source and the drain of the third transistor is electrically connected to a third terminal. A first capacitor is provided between the first node and the second node. An inverting input of the comparator is electrically connected to a fourth terminal. An output of the comparator is electrically connected to a fifth terminal.
    Type: Application
    Filed: March 16, 2020
    Publication date: June 16, 2022
    Inventors: Takayuki IKEDA, Takeshi AOKI, Munehiro KOZUMA, Kei TAKAHASHI, Shunpei YAMAZAKI
  • Patent number: 11358398
    Abstract: There is provided a print control device that causes a printing device to perform printing, the print control device including: a specifying section that specifies a print target from a captured image captured by an image capturing sensor; a display section that displays, on a display, a screen in which a trimmed image is superimposed on the captured image, the trimmed image being obtained by trimming a preview image of original print data in accordance with the print target; a setting receiving section that receives a setting of a relative position of the preview image with respect to the print target; a print instruction receiving section that receives a print instruction at the relative position; and a control section that causes the printing device to perform printing on the print target based on the original print data and the relative position according to the print instruction.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Seiko Epson Corporation
    Inventors: Hiroaki Nakanishi, Ikuo Masujima, Kiyokazu Kamijo, Kei Miyazawa, Takahiro Otani, Junko Yamamoto, Takeshi Aoki, Akinobu Miyasaka, Shiori Naruse