Abstract: A flow conversion system for a manufacturing process includes a flow decomposition module decomposing a process in a target process flow into lower processes based on a process decomposition table to create an intermediate lower process flow; a compatible flow generation module replacing the lower processes with a lower compatible process based on a lower process compatibility table to create an intermediate lower compatible process flow; a flow check module creating a lower process flow including all the lower processes available in production facilities from the intermediate and intermediate lower compatible process flows based on an available process table; a flow selection module selecting the lower process flow by calculating an attribute based on an attribute definition table. An external storage unit stores the process decomposition table, the lower process compatibility table, the available process table, and the attribute definition table.

Abstract: A flow conversion system for a manufacturing process includes a flow decomposition module decomposing a process in a target process flow into lower processes based on a process decomposition table to create an intermediate lower process flow; a compatible flow generation module replacing the lower processes with a lower compatible process based on a lower process compatibility table to create an intermediate lower compatible process flow; a flow check module creating a lower process flow including all the lower processes available in production facilities from the intermediate and intermediate lower compatible process flows based on an available process table; a flow selection module selecting the lower process flow by calculating an attribute based on an attribute definition table. An external storage unit stores the process decomposition table, the lower process compatibility table, the available process table, and the attribute definition table.

Abstract: A semiconductor device includes a semiconductor substrate having a first and a second region, a first wiring layer including a lower layer having polycrystal silicon portions including impurities at a high concentration and formed over the first region of the semiconductor substrate via an insulating film. An upper layer of the first wiring layer is a metal silicide having a first film thickness. A second wiring layer includes a lower layer formed over the second region of the semiconductor substrate via an insulating film and is formed of either a non-doped polycrystal portion or a polycrystal silicon portion having a resistivity of at least 10 &OHgr;cm. An upper layer of the second wiring layer is a metal silicide portion having a second film thickness thicker than the first film thickness.

Abstract: The present invention provides a semiconductor integrated circuit having excellent junction characteristics when applying the silicide technology to an extremely narrowed diffusion layer between adjacent gate electrodes as well as a method for manufacturing the same. To attain this object, a configuration of the invention has electrode layers formed on a semiconductor substrate, sidewall layers formed on the side walls of electrode layers, and high-melting point metal silicide layers formed on the electrode layers, wherein the sidewall layers are connected together. This makes it possible to eliminate abnormal growth during silicide formation because of the fact that the region defined between the electrode layers on the substrate is covered by the sidewall layers.

Abstract: The present invention provides a semiconductor integrated circuit having excellent junction characteristics when applying the silicide technology to an extremely narrowed diffusion layer between adjacent gate electrodes as well as a method for manufacturing the same. To attain this object, a configuration of the invention has electrode layers formed on a semiconductor substrate, sidewall layers formed on the side walls of electrode layers, and high-melting point metal silicide layers formed on the electrode layers, wherein the sidewall layers are connected together. This makes it possible to eliminate abnormal growth during silicide formation because of the fact that the region defined between the electrode layers on the substrate is covered by the sidewall layers.

Abstract: The present invention provides a semiconductor integrated circuit having excellent junction characteristics when applying the silicide technology to an extremely narrowed diffusion layer between adjacent gate electrodes as well as a method for manufacturing the same. To attain this object, a configuration of the invention has electrode layers formed on a semiconductor substrate, sidewall layers formed on the side walls of electrode layers, and high-melting point metal silicide layers formed on the electrode layers, wherein the sidewall layers are connected together. This makes it possible to eliminate abnormal growth during silicide formation because of the fact that the region defined between the electrode layers on the substrate is covered by the sidewall layers.

Abstract: The present invention provides a semiconductor integrated circuit having excellent junction characteristics when applying the silicide technology to an extremely narrowed diffusion layer between adjacent gate electrodes as well as a method for manufacturing the same. To attain this object, a configuration of the invention has electrode layers formed on a semiconductor substrate, sidewall layers formed on the side walls of electrode layers, and high-melting point metal silicide layers formed on the electrode layers, wherein the sidewall layers are connected together. This makes it possible to eliminate abnormal growth during silicide formation because of the fact that the region defined between the electrode layers on the substrate is covered by the sidewall layers.

Abstract: A semiconductor device includes a semiconductor substrate having a first and a second region, a first wiring layer including a lower layer having polycrystal silicon portions including impurities at a high concentration and formed over the first region of the semiconductor substrate via an insulating film. An upper layer of the first wiring layer is a metal silicide having a first film thickness. A second wiring layer includes a lower layer formed over the second region of the semiconductor substrate via an insulating film and is formed of either a non-doped polycrystal portion or a polycrystal silicon portion having a resistivity of at least 10 &OHgr;cm. An upper layer of the second wiring layer is a metal silicide portion having a second film thickness thicker than the first film thickness.

Abstract: The present invention relates to a semiconductor device wherein a dummy gate electrode is fixed to the same electric potential as that of a substrate, the stable operation of an LSI is maintained and the process margin is large, and also to a producing method of the semiconductor device, and the semiconductor device comprises a P-type silicon substrate, a dummy element region unnecessary for the actual LSI operation, which is formed on the P-type silicon substrate, and a dummy gate electrode unnecessary for the actual LSI operation, which is formed on at least a part of the dummy element region through a dummy oxide film, wherein by selectively forming titanium silicide on at least a part of a surface of the dummy element region and the dummy gate electrode, a P.sup.+ -diffusion layer and a P.sup.+ -dummy gate electrode of the dummy element region are short-circuited by titanium silicide.