Patents by Inventor Takeshi Fukazawa
Takeshi Fukazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190391395Abstract: An additional service that can make eating more enjoyable for a customer in an eating facility is provided. A head-mounted display which is worn by a customer in a facility in which food is offered includes: a display unit that displays image content; an acquisition unit that sequentially acquires an image of predetermined food which is captured by an imaging device; a determination unit that determines whether the image of the food acquired at the time of second acquisition by the acquisition unit varies from the image of the food acquired at the time of first acquisition by the acquisition unit; and an image processing unit that adds a first predetermined variation to the image content when the determination unit has determined that the image of the food acquired at the time of second acquisition varies from the image of the food acquired at the time of first acquisition.Type: ApplicationFiled: June 19, 2019Publication date: December 26, 2019Applicant: Tyffon Inc.Inventor: Takeshi FUKAZAWA
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Patent number: 10322342Abstract: Provided is an image output device including image acquisition means for acquiring an image related to a subject captured by a user, position information acquisition means for acquiring position information indicating a position where the image is captured, generation means for generating a landscape image in which an image based on the image acquired by the image acquisition means is superimposed on an image obtained by capturing the landscape, when displaying the image obtained by capturing the landscape of position information acquired by the position information acquisition means, and image output means for outputting the landscape image.Type: GrantFiled: October 30, 2015Date of Patent: June 18, 2019Assignee: Tyffon Inc.Inventors: Takeshi Fukazawa, Teruyuki Nakahashi
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Patent number: 9853168Abstract: A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.Type: GrantFiled: September 23, 2016Date of Patent: December 26, 2017Assignee: DENSO CORPORATIONInventor: Takeshi Fukazawa
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Patent number: 9583642Abstract: A diode has a multiple p-n junction body, anode and cathode electrodes, a short-circuit electrode, a guard ring, and an insulation film. The multiple p-n junction body has first to fourth semiconductor layers stacked to provide a lamination structure between the anode electrode and the cathode electrode. Each of the first and third semiconductor layers is a first conductive semiconductor. Each of the second and fourth semiconductor layers is a second conductive semiconductor. The first and second semiconductor layers form a p-n junction. The second and third semiconductor layers form a p-n junction. The third and fourth semiconductor layers form a p-n junction. The short circuit electrode provides a short circuit between the second semiconductor layer and the third semiconductor layer. A high concentration region is formed in a contact region in the second semiconductor layer. A surface of the contact region is in contact with the short-circuit electrode.Type: GrantFiled: November 10, 2015Date of Patent: February 28, 2017Assignee: DENSO CORPORATIONInventor: Takeshi Fukazawa
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Publication number: 20170012140Abstract: A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.Type: ApplicationFiled: September 23, 2016Publication date: January 12, 2017Inventor: Takeshi FUKAZAWA
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Patent number: 9478672Abstract: A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.Type: GrantFiled: August 6, 2013Date of Patent: October 25, 2016Assignee: DENSO CORPORATIONInventor: Takeshi Fukazawa
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Publication number: 20160133757Abstract: A diode has a multiple p-n junction body, anode and cathode electrodes, a short-circuit electrode, a guard ring, and an insulation film. The multiple p-n junction body has first to fourth semiconductor layers stacked to provide a lamination structure between the anode electrode and the cathode electrode. Each of the first and third semiconductor layers is a first conductive semiconductor. Each of the second and fourth semiconductor layers is a second conductive semiconductor. The first and second semiconductor layers form a p-n junction. The second and third semiconductor layers form a p-n junction. The third and fourth semiconductor layers form a p-n junction. The short circuit electrode provides a short circuit between the second semiconductor layer and the third semiconductor layer. A high concentration region is formed in a contact region in the second semiconductor layer. A surface of the contact region is in contact with the short-circuit electrode.Type: ApplicationFiled: November 10, 2015Publication date: May 12, 2016Inventor: Takeshi FUKAZAWA
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Publication number: 20160121215Abstract: Provided is an image output device including image acquisition means for acquiring an image related to a subject captured by a user, position information acquisition means for acquiring position information indicating a position where the image is captured, generation means for generating a landscape image in which an image based on the image acquired by the image acquisition means is superimposed on an image obtained by capturing the landscape, when displaying the image obtained by capturing the landscape of position information acquired by the position information acquisition means, and image output means for outputting the landscape image.Type: ApplicationFiled: October 30, 2015Publication date: May 5, 2016Inventors: Takeshi Fukazawa, Teruyuki Nakahashi
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Publication number: 20140034967Abstract: A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.Type: ApplicationFiled: August 6, 2013Publication date: February 6, 2014Applicant: DENSO CORPORATIONInventor: Takeshi FUKAZAWA
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Patent number: 7420246Abstract: A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.Type: GrantFiled: May 30, 2006Date of Patent: September 2, 2008Assignee: DENSO CORPORATIONInventors: Shoji Ozoe, Tomofusa Shiga, Yoshifumi Okabe, Takaaki Aoki, Takeshi Fukazawa, Kimiharu Kayukawa
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Patent number: 7197742Abstract: The present invention relates to a software module, and, especially, relates to a software module for integration having severe restriction on the available memory amount and the real-time operation, and provides a software module for integration having increased inheritance in software. This is a software module for integration, integrated as a software module within a device to control the device. The software module has a public module for updating a public data value, an intermediate module for converting the data value in a predetermined data format updated in the public module into a data value in a predetermined data format adaptable to a referencing side, and a referencing module for referencing the data value in a predetermined data format converted by the intermediate module. The publication and referencing process can be implemented among the modules.Type: GrantFiled: February 7, 2002Date of Patent: March 27, 2007Assignee: Fujitsu Ten LimitedInventors: Hiroshi Arita, Akira Ikezoe, Kiyoshi Yagi, Minoru Takahashi, Takeshi Fukazawa
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Publication number: 20060273351Abstract: A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.Type: ApplicationFiled: May 30, 2006Publication date: December 7, 2006Applicant: DENSO CORPORATIONInventors: Shoji Ozoe, Tomofusa Shiga, Yoshifumi Okabe, Takaaki Aoki, Takeshi Fukazawa, Kimiharu Kayukawa
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Publication number: 20030106044Abstract: The present invention relates to a software module, and, especially, relates to a software module for integration having severe restriction on the available memory amount and the real-time operation, and provides a software module for integration having increased inheritance in software. This is a software module for integration, integrated as a software module within a device to control the device. The software module has a public module for updating a public data value, an intermediate module for converting the data value in a predetermined data format updated in the public module into a data value in a predetermined data format adaptable to a referencing side, and a referencing module for referencing the data value in a predetermined data format converted by the intermediate module. The publication and referencing process can be implemented among the modules.Type: ApplicationFiled: October 23, 2002Publication date: June 5, 2003Inventors: Hiroshi Arita, Akira Ikezoe, Kiyoshi Yagi, Minoru Takahashi, Takeshi Fukazawa
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Patent number: 6316300Abstract: A method of manufacturing of a semiconductor device having a thermal oxidation process for selectively forming an oxide film by a thermal oxidation, which can reduce the generation of lattice defects in the semiconductor device during the thermal oxidation process. A groove portion LOCOS oxide film is formed in a groove portion of a semiconductor substrate by first and second wet oxidation steps. At the first wet oxidation step, a thin oxide film is formed on an exposed surface of an epitaxial layer by performing a wet oxidation through an opening portion made of silicon nitride under an oxidation temperature of approximately 875° C. At the second wet oxidation step, the oxidation temperature is risen to approximately 1050° C. to advance the oxidation of the epitaxial layer to finally form the groove portion LOCOS oxide film having a thickness of approximately 950 nm.Type: GrantFiled: September 8, 1999Date of Patent: November 13, 2001Assignee: Denso CorporationInventors: Yoshihiko Ozeki, Yoshifumi Okabe, Takeshi Fukazawa, Hisanori Yokura
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Patent number: 5877095Abstract: A semiconductor device includes a semiconductor element. A silicon nitride film covers the semiconductor element. The silicon nitride film is made of Si.sub.X N.sub.Y H.sub.Z, where X, Y, and Z denote atomic fractions of Si, N, and H resptively. The silicon nitride film relates to an optical absorption edge wavelength shorter than 254 nm. A mean area of regions surrounded by crystal-like grain boundaries at a surface of the silicon nitride film is equal to 4.5.times.10.sup.4 nm.sup.2 or more. The semiconductor element may include a memory element from which information can be erased by exposure to ultraviolet rays.Type: GrantFiled: August 16, 1996Date of Patent: March 2, 1999Assignee: Nippondenso Co., Ltd.Inventors: Muneo Tamura, Takeshi Yamauchi, Katuhide Niwa, Takeshi Fukazawa, Akira Kuroyanagi
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Patent number: 5714781Abstract: A power MOSFET having a groove for forming a channel improved for shortening the switching time and increasing the dielectric breakdown strength of the gate oxide film is disclosed. The power MOSFET includes a concave structure in which a gate oxide film at a groove bottom is thickened. Namely, since the gate oxide film between a gate electrode and a first conductivity type semiconductor layer is thick, the capacitance of the oxide film therebetween is reduced. Therefore, the input and output capacitance of the gate oxide film can be reduced, and switching loss can be also reduced since the switching time can be shortened. Further, greater dielectric breakdown strength of the gate oxide film can be obtained as a result of the thickened gate oxide film at the groove bottom.Type: GrantFiled: April 26, 1996Date of Patent: February 3, 1998Assignee: Nippondenso Co., Ltd.Inventors: Tsuyoshi Yamamoto, Masami Naito, Takeshi Fukazawa
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Patent number: 5610856Abstract: An increase in the GND resistance and a drop in the resistance against electromigration are minimized when the ground voltage lines for shunting are finely constituted by using an Al wiring of the same layer as the pad layer, owing to the employment of a layout in which the arrangement of connection holes 24, 26 in a pad layer connected to one (data line) of the complementary data lines and the arrangement of connection holes in a pad layer connected to the other one (data line bar) of the complementary data lines, are inverted from each other every two bits of memory cells in the SRAM along the direction in which the complementary data lines extend.Type: GrantFiled: March 4, 1996Date of Patent: March 11, 1997Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Keiichi Yoshizumi, Satoru Haga, Shuji Ikeda, Kiichi Makuta, Takeshi Fukazawa
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Patent number: 5592004Abstract: A semiconductor device includes a semiconductor element. A silicon nitride film covers the semiconductor element. The silicon nitride film is made of Si.sub.X N.sub.Y H.sub.Z, where X, Y, and Z denote atomic fractions of Si, N, and H respectively. The silicon nitride film relates to an optical absorption edge wavelength shorter than 254 nm. A mean area of regions surrounded by crystal-like grain boundaries at a surface of the silicon nitride film is equal to 4.5.times.10.sup.4 nm.sup.2 or more. The semiconductor element may include a memory element from which information can be erased by exposure to ultraviolet rays.Type: GrantFiled: September 28, 1995Date of Patent: January 7, 1997Assignee: Nippondenso Co., Ltd.Inventors: Muneo Tamura, Takeshi Yamauchi, Katuhide Niwa, Takeshi Fukazawa, Akira Kuroyanagi, Tooru Yamaoka
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Patent number: 5373471Abstract: In case an address is to access a defective memory cell, a defective memory cell in a memory cell area contained in one of paired memory mats is selected in parallel with a redundant memory cell in a redundant memory cell area contained in the other memory mat. At this time of selecting the redundant main word line for selecting the redundant memory cell, there is not required the logical operation for deciding whether or not the redundant use of the access address fed from the outside is proper. For example, the redundant main word line is set to the select level on the basis of a chip select signal. As a result, the drive start timing of the redundant main word line is not delayed in the least from the drive start timing of the main word line. Thus, it is possible to prevent the event that the select drive timing of the redundant sub word line is delayed on account of the delay in the drive timing of the redundant main word line.Type: GrantFiled: August 25, 1992Date of Patent: December 13, 1994Assignee: Hitachi, Ltd.Inventors: Makoto Saeki, Kiyoshi Nagai, Hisae Yamamura, Tadashi Abe, Takeshi Fukazawa
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Patent number: 4881056Abstract: A facedown-type semiconductor pressure sensor has a Si sensing element including a diaphragm, a spacer, and a piezoresistive device embedded in the diaphragm, and a pedestal. The spacer, which is positioned between the semiconductor substrate and the pedestal, has a photolitho-graphically etched hole such that the sensing element, the hole and the pedestal define a sealed chamber. The sealed pressure chamber is substantially aligned with the diaphragm.Type: GrantFiled: April 11, 1988Date of Patent: November 14, 1989Assignee: Nippondenso Co., Ltd.Inventors: Masahito Mizukoshi, Eishi Kawasaki, Takeshi Miyajima, Takeshi Fukazawa