Patents by Inventor Takeshi Kaizuka

Takeshi Kaizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6436203
    Abstract: The present invention provides a CVD apparatus and a CVD method for use in forming an Al/Cu multilayered film. The Al/Cu multilayered film is formed in the CVD apparatus comprising a chamber for placing a semiconductor wafer W, a susceptor for mounting the semiconductor wafer W thereon, an Al raw material supply system for introducing a gasified Al raw material into the chamber and a Cu raw material supply system for introducing a gasified Cu raw material into the chamber. The Al/Cu multilayered film is formed by repeating a series of steps consisting of introducing the Al raw material gas into the chamber, depositing the Al film on the semiconductor wafer W by a CVD method, followed by generating a plasma in the chamber in which the Cu raw material gas has been introduced and depositing the Cu film on the semiconductor wafer W by a CVD method. The Al/Cu multilayered film thus obtained is subjected to a heating treatment (annealing), thereby forming a desired Al/Cu multilayered film.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: August 20, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Takeshi Kaizuka, Takashi Horiuchi, Masami Mizukami, Takashi Mochizuki, Yumiko Kawano, Hideaki Yamasaki
  • Patent number: 6089184
    Abstract: The present invention provides a CVD apparatus and a CVD method for use in forming an Al/Cu multilayered film. The Al/Cu multilayered film is formed in the CVD apparatus comprising a chamber for placing a semiconductor wafer W, a susceptor for mounting the semiconductor wafer W thereon, an Al raw material supply system for introducing a gasified Al raw material into the chamber and a Cu raw material supply system for introducing a gasified Cu raw material into the chamber. The Al/Cu multilayered film is formed by repeating a series of steps consisting of introducing the Al raw material gas into the chamber, depositing the Al film on the semiconductor wafer W by a CVD method, followed by generating a plasma in the chamber in which the Cu raw material gas has been introduced and depositing the Cu film on the semiconductor wafer W by a CVD method. The Al/Cu multilayered film thus obtained is subjected to a heating treatment (annealing), thereby forming a desired Al/Cu multilayered film.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: July 18, 2000
    Assignee: Tokyo Electron Limited
    Inventors: Takeshi Kaizuka, Takashi Horiuchi, Masami Mizukami, Takashi Mochizuki, Yumiko Kawano, Hideaki Yamasaki
  • Patent number: 6063703
    Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connecting holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: May 16, 2000
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Takeshi Kaizuka, Nobuyuki Takeyasu, Tomohiro Ohta, Eiichi Kondoh, Hiroshi Yamamoto, Tomoharu Katagiri, Tadashi Nakano, Yumiko Kawano
  • Patent number: 6001736
    Abstract: An insulating layer is provided on a semiconductor substrate, a contact hole is formed in the insulating layer, and an underlying metal film is provided on a whole surface of the substrate including inner walls of the contact hole. A surface condition of the underlying metal film is adjusted by a hydrogen plasma treatment. By the hydrogen plasma treatment, a surface of the underlying metal film is hydrogenated and is sputter-etched, so that a disordered film and contaminants adsorbed on the surface of the underlying metal film are removed. Next, aluminum is deposited on the underlying metal film by a chemical vapor deposition process using an organic aluminum compound such as DMAH. The contact hole can be effectively filled with aluminum.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: December 14, 1999
    Assignees: Kawasaki Steel Corporation, Tokyo Electron Limited
    Inventors: Eiichi Kondo, Nobuyuki Takeyasu, Tomohiro Ohta, Yumiko Kawano, Takeshi Kaizuka, Shinpei Jinnouchi
  • Patent number: 5973402
    Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.
    Type: Grant
    Filed: January 30, 1997
    Date of Patent: October 26, 1999
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Takeshi Kaizuka, Nobuyuki Takeyasu, Tomohiro Ohta, Eiichi Kondoh, Hiroshi Yamamoto, Tomoharu Katagiri, Tadashi Nakano, Yumiko Kawano
  • Patent number: 5627102
    Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: May 6, 1997
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Takeshi Kaizuka, Nobuyuki Takeyasu, Tomohiro Ohta, Eiichi Kondoh, Hiroshi Yamamoto, Tomoharu Katagiri, Tadashi Nakano, Yumiko Kawano
  • Patent number: 5521423
    Abstract: An antifuse element suitable for use in FPGA. When a device is miniaturized to reduce the write voltage in an antifuse element and as the film thickness of the antifuse dielectric film is being reduced, the dielectric breakdown voltage is greatly variable due to the irregularity of the underlying metal. If the dielectric film is formed by a metal oxide having a relatively high specific permitivity without changing its parasitic capacity as compared to the prior art, the film thickness of the dielectric film can be increased in comparison with oxide and nitride films formed according to the prior art. The irregularity of the underlying metal can be reduced by coating it with a metal nitride or TiB film or TiC film. To equalize the dielectric breakdown voltage, another insulation film having a film thickness such that the direct tunnel conduction is dominant is formed below the metal oxide.
    Type: Grant
    Filed: April 15, 1994
    Date of Patent: May 28, 1996
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Takeshi Kaizuka, Tomohiro Ohta