Patents by Inventor Takeshi Kamigaichi

Takeshi Kamigaichi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230328991
    Abstract: A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: KIOXIA CORPORATION
    Inventor: Takeshi KAMIGAICHI
  • Patent number: 11716852
    Abstract: A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: August 1, 2023
    Assignee: Kioxia Corporation
    Inventor: Takeshi Kamigaichi
  • Publication number: 20220375960
    Abstract: A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape
    Type: Application
    Filed: August 4, 2022
    Publication date: November 24, 2022
    Applicant: Kioxia Corporation
    Inventor: Takeshi KAMIGAICHI
  • Patent number: 11444102
    Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: September 13, 2022
    Assignee: Kioxia Corporation
    Inventor: Takeshi Kamigaichi
  • Publication number: 20210391344
    Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki KUTSUKAKE, Kikuko SUGIMAE, Takeshi KAMIGAICHI
  • Patent number: 11133323
    Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 28, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Kutsukake, Kikuko Sugimae, Takeshi Kamigaichi
  • Publication number: 20210183888
    Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
    Type: Application
    Filed: February 25, 2021
    Publication date: June 17, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi KAMIGAICHI
  • Patent number: 10964719
    Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Kamigaichi
  • Patent number: 10861789
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Publication number: 20200168546
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 28, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto MIZUKAMI, Takeshi KAMIGAICHI
  • Patent number: 10608009
    Abstract: This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Keiji Ikeda, Masumi Saitoh, Hideaki Aochi, Takeshi Kamigaichi, Jun Fujiki
  • Patent number: 10535604
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: January 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Publication number: 20190386020
    Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
    Type: Application
    Filed: August 27, 2019
    Publication date: December 19, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi KAMIGAICHI
  • Patent number: 10446576
    Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Kamigaichi
  • Publication number: 20190103412
    Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroyuki KUTSUKAKE, Kikuko Sugimae, Takeshi Kamigaichi
  • Patent number: 10170489
    Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Kutsukake, Kikuko Sugimae, Takeshi Kamigaichi
  • Publication number: 20180323210
    Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
    Type: Application
    Filed: June 28, 2018
    Publication date: November 8, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi KAMIGAICHI
  • Publication number: 20180301415
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Application
    Filed: June 21, 2018
    Publication date: October 18, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 10056333
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: August 21, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 10043823
    Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: August 7, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Kamigaichi