Patents by Inventor Takeshi Kinjo
Takeshi Kinjo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8592816Abstract: A thin film transistor matrix device including an insulating substrate with a plurality of lines arranged on the substrate, where the lines include first lines and second lines. The device also includes a first connection line extending in a direction transverse to the plurality of lines, where the first connection line and the first lines are configured and arranged to be electrically connected to each other, as well as a second connection line extending in a direction transverse to the plurality of lines, where the second connection line and the second lines are also configured and arranged to be electrically connected to each other. The first and second connection lines are both formed on the same side of an image display region, when considered in plan view. Finally, the plurality of lines are associated, respectively, with drain bus lines and/or gate bus lines.Type: GrantFiled: July 19, 2012Date of Patent: November 26, 2013Assignee: Sharp Kabushiki KaishaInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Publication number: 20130015451Abstract: A thin film transistor matrix device including an insulating substrate; a plurality of lines arranged on the substrate, with the lines being defined as odd-number-th lines alternating with even-number-th lines; a first connection line extending in a direction transverse to the plurality of lines, where the first connection line and the odd-number-th lines are configured and arranged to be electrically connected/disconnected to/from each other; and a second connection line extending in a direction transverse to the plurality of lines, where the second connection line and the ven-number-th lines are configured and arranged to be electrically connected/disconnected to/from each other.Type: ApplicationFiled: July 19, 2012Publication date: January 17, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Patent number: 8258513Abstract: A thin film transistor matrix device including an insulating substrate and a plurality of lines arranged on the substrate. The lines are defined as odd-number-th lines alternating with even-number-th lines. A first connection line extends in a direction transverse to the plurality of lines. The first connection line and the odd-number-th lines are configured and arranged to be electrically connected to each other. A second connection line extends in a direction transverse to the plurality of lines. The second connection line and the even-number-th lines are configured and arranged to be electrically connected to each other. The first connection line and the second connection line are both formed on the same side of an image display region, when considered in plan view.Type: GrantFiled: April 29, 2010Date of Patent: September 4, 2012Assignee: Sharp Kabushiki KaishaInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Patent number: 7947982Abstract: A thin film transistor matrix device including an insulating substrate, a plurality of thin film transistors (TFTs) on the insulating substrate, and a plurality of picture element electrodes (connected to the TFTs) on the insulating substrate in a matrix to define an image display region. A first conductor is on the insulating substrate. A first insulating film is on the first conductor, a second conductor is on the first insulating film, and a second insulating film is over the first insulating film and the second conductor. A first contact hole is formed in the first and second insulating films, a second contact hole is formed in the second insulating film, and a conducting connection is formed between the first and second contact holes. The first and second conductors are connected to the conducting connection via the first and second contact holes, respectively, which are both outside the image display region.Type: GrantFiled: June 22, 2009Date of Patent: May 24, 2011Assignee: Sharp Kabushiki KaishaInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Patent number: 7947983Abstract: A thin film transistor matrix device including an insulating substrate, a plurality of thin film transistors (TFTs) on the insulating substrate, and a plurality of picture element electrodes on the insulating substrate in a matrix to define an image display region. A first conducting film is on the insulating substrate. A first insulating film is on the first conducting film. A second conducting film is on the first insulating film, and a second insulating film is over the first insulating film and the second conducting film. A first conducting connection is formed, outside the image display region, to pass through the first and second insulating films, and to electrically connect the first conducting film to a third conducting film. A second conducting connection is formed, outside the image display region, to pass through the second insulating film and to electrically connect the second conducting film to the third conducting film.Type: GrantFiled: January 15, 2010Date of Patent: May 24, 2011Assignee: Sharp Kabushiki KaishaInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Publication number: 20100214202Abstract: A method for fabricating a thin film transistor matrix device which includes forming a transparent insulating substrate, arranging a plurality of thin film transistors on the substrate in a matrix, arranging a plurality of picture element electrodes on the substrate in a matrix and connecting the picture element electrodes to sources of the thin film transistors. The method also includes forming a plurality of bus lines for commonly connecting gates or drains of the thin film transistors, forming a plurality of bus line terminals on the ends of the bus lines, respectively, with each bus line terminal being provided for each bus line, and forming one connection line on the substrate in a region outer of plurality of the bus line terminals and commonly connecting the plurality of bus lines. The method further includes the step of electrically disconnecting the bus lines from the connection line by laser melting.Type: ApplicationFiled: April 29, 2010Publication date: August 26, 2010Applicant: SHARP KABUSHIKI KAISHAInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Publication number: 20100117087Abstract: A method for fabricating a thin film transistor matrix device which includes forming a transparent insulating substrate, arranging a plurality of thin film transistors on the substrate in a matrix, arranging a plurality of picture element electrodes on the substrate in a matrix and connecting the picture element electrodes to sources of the thin film transistors. The method also includes forming a plurality of bus lines for commonly connecting gates or drains of the thin film transistors, forming a plurality of bus line terminals on the ends of the bus lines, respectively, with each bus line terminal being provided for each bus line, and forming one connection line on the substrate in a region outer of plurality of the bus line terminals and commonly connecting the plurality of bus lines. The method further includes the step of electrically disconnecting the bus lines from the connection line by laser melting.Type: ApplicationFiled: January 15, 2010Publication date: May 13, 2010Applicant: SHARP KABUSHIKI KAISHAInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Publication number: 20090256153Abstract: A method for fabricating a thin film transistor matrix device which includes forming a transparent insulating substrate, arranging a plurality of thin film transistors on the substrate in a matrix, arranging a plurality of picture element electrodes on the substrate in a matrix and connecting the picture element electrodes to sources of the thin film transistors. The method also includes forming a plurality of bus lines for commonly connecting gates or drains of the thin film transistors, forming a plurality of bus line terminals on the ends of the bus lines, respectively, with each bus line terminal being provided for each bus line, and forming one connection line on the substrate in a region outer of plurality of the bus line terminals and commonly connecting the plurality of bus lines. The method further includes the step of electrically disconnecting the bus lines from the connection line by laser melting.Type: ApplicationFiled: June 22, 2009Publication date: October 15, 2009Applicant: SHARP KABUSHIKI KAISHAInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Patent number: 7575960Abstract: A method for fabricating a thin film transistor matrix device which includes forming a transparent insulating substrate, arranging a plurality of thin film transistors on the substrate in a matrix, arranging a plurality of picture element electrodes on the substrate in a matrix and connecting the picture element electrodes to sources of the thin film transistors. The method also includes forming a plurality of bus lines for commonly connecting gates or drains of the thin film transistors, forming a plurality of bus line terminals on the ends of the bus lines, respectively, with each bus line terminal being provided for each bus line, and forming one connection line on the substrate in a region outer of plurality of the bus line terminals and commonly connecting the plurality of bus lines. The method further includes the step of electrically disconnecting the bus lines from the connection line by laser melting.Type: GrantFiled: March 16, 2006Date of Patent: August 18, 2009Assignee: Sharp Kabushiki KaishaInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Publication number: 20060163579Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: ApplicationFiled: March 16, 2006Publication date: July 27, 2006Inventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Patent number: 7075108Abstract: A thin film transistor matrix device including an insulating substrate, a plurality of thin film transistors arranged on the insulating substrate, and a plurality of picture element electrodes arranged on the insulating substrate in a matrix and connected to the thin film transistors. The device also includes a plurality of bus lines made of a first conducting film, a first insulating film formed on the first conducting film, a second conducting film formed on the first insulating film, and a second insulating film formed on the first insulating film and the second conducting film. Additionally, first and second contact holes are formed outside an image display region in which the plurality of picture elements are formed. The first conducting film is connected to the third conducing film via the first contact hole, and the second conducting film is connected to the third conducting film via the second contact hole.Type: GrantFiled: September 11, 2003Date of Patent: July 11, 2006Assignee: Fujitsu LimitedInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Patent number: 6767754Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall televisions. On a transparent insulating substrate there are formed gate bus lines for commonly connecting the gates of thin film transistors, drain bus lines for commonly connecting the drains of the thin film transistors, and outside terminals opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines for commonly connecting the gate bus lines, and drain connection lines for commonly connecting the drain bus lines, are formed on the transparent insulating substrate in regions inner of the outside terminals. The thin film transistor matrix device can be fabricate without occurrence of short circuit defects, with little characteristic change, and with high yields.Type: GrantFiled: February 21, 2002Date of Patent: July 27, 2004Assignee: Fujitsu Display Technologies CorporationInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Publication number: 20040046175Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: ApplicationFiled: September 11, 2003Publication date: March 11, 2004Applicant: FUJITSU DISPLAY TECHNOLOGIES CORPORATIONInventors: Hideaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Publication number: 20020084460Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the-gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: ApplicationFiled: February 21, 2002Publication date: July 4, 2002Applicant: FUJITSU LIMITEDInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Patent number: 6406946Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TV's. On a transparent insulating substrate there are formed gate bus lines for commonly connecting the gates of thin film transistors, drain bus lines for commonly connecting the drains of the thin film transistors, and outside terminals and outside terminals opposed respectively to the ends of the gate bus lines and the drain bus lines, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines for commonly connecting the gate bus lines and drain connection lines for commonly connecting the drain bus lines are formed on the transparent insulating substrate in regions inner of the outside terminals. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: GrantFiled: January 8, 1998Date of Patent: June 18, 2002Assignee: Fujitsu LimitedInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
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Publication number: 20020028540Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: ApplicationFiled: January 8, 1998Publication date: March 7, 2002Inventors: HIDAKI TAKIZAWA, SHOUGO HAYASHI, TAKESHI KINJO, MAKOTO TACHIBANAKI, KENJI OKAMOTO
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Patent number: 5742074Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal coputers and wall TV's. On a transparent insulating substrate there are formed gate bus lines for commonly connecting the gates of thin film transistors, drain bus lines for commonly connecting the drains of the thin film transistors, and outside terminals and outside terminals opposed respectively to the ends of the gate bus lines and the drain bus lines, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines for commonly connecting the gate bus lines and drain connection lines for commonly connecting the drain bus lines are formed on the transparent insulating substrate in regions inner of the outside terminals. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: GrantFiled: May 29, 1996Date of Patent: April 21, 1998Assignee: Fujitsu LimitedInventors: Hidaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto