Abstract: A semiconductor device, a signal processing system, and a signal processing method are provided that regulate a change of characteristics in the event of aged deterioration. The semiconductor device of the present invention includes a reference voltage generation circuit that generates a reference voltage, an analog signal processing circuit that outputs a first processing signal according to the reference voltage, a test signal output section that outputs, as a test signal, a second processing signal having a lower voltage than the first processing signal, an input section that receives a regulation signal for the outputted test signal, and a regulator circuit that regulates the output of the analog signal processing circuit in response to the regulation signal.

Abstract: A semiconductor device, a signal processing system, and a signal processing method are provided that regulate a change of characteristics in the event of aged deterioration. The semiconductor device of the present invention includes a reference voltage generation circuit that generates a reference voltage, an analog signal processing circuit that outputs a first processing signal according to the reference voltage, a test signal output section that outputs, as a test signal, a second processing signal having a lower voltage than the first processing signal, an input section that receives a regulation signal for the outputted test signal, and a regulator circuit that regulates the output of the analog signal processing circuit in response to the regulation signal.

Abstract: A semiconductor device capable of preventing deterioration of a transistor caused by a flow of an overcurrent is provided. According to an embodiment, a semiconductor chip includes a first transistor provided between a high-potential side voltage terminal to which a constant voltage generated by reducing a power-supply voltage is supplied and an output terminal, a second transistor provided between a low-potential side voltage terminal to which a ground voltage is supplied and the output terminal, a control circuit controlling turning-on/off of the first and second transistors, a boosting circuit boosting the power-supply voltage by using a voltage of the output terminal to generate an output voltage, and an overvoltage detection circuit detecting an overvoltage of a power-supply line that couples the high-potential side voltage terminal and the first transistor to each other. The control circuit performs control to turn off the second transistor, when the overvoltage has been detected.

Abstract: A semiconductor device capable of preventing deterioration of a transistor caused by a flow of an overcurrent is provided. According to an embodiment, a semiconductor chip includes a first transistor provided between a high-potential side voltage terminal to which a constant voltage generated by reducing a power-supply voltage is supplied and an output terminal, a second transistor provided between a low-potential side voltage terminal to which a ground voltage is supplied and the output terminal, a control circuit controlling turning-on/off of the first and second transistors, a boosting circuit boosting the power-supply voltage by using a voltage of the output terminal to generate an output voltage, and an overvoltage detection circuit detecting an overvoltage of a power-supply line that couples the high-potential side voltage terminal and the first transistor to each other. The control circuit performs control to turn off the second transistor, when the overvoltage has been detected.

Abstract: A device for stopping a flow of fluid in a fixed length of tube with an actuator simple in construction is provided. The stopping device is free of direct touch with the fluid inside the tube, expected not to obstruct the flow in the tube as permitted as possible at normal condition, expected to perform both detection and control with a single device, and further invulnerable to kinds of fluids. The device for stopping a flow of fluid includes a tube holder to keep a tube in looped configuration, a movable part pressing the looped configuration of the tube. Pressing of the looped configuration of the tube make a snapped bent to stop the flow of fluid passed through the tube. Putting the movable part back into place results in the tube's returning from the configuration having the bent, allowing the fluid flowing again through the tube.

Abstract: The invention provides a transceiver circuit for communication that enhances the operation frequency of a synchronous digital circuit up to the maximum frequency of a flip-flop and inhibits the occurrence of jitters. A clock signal synchronized with data at f1/n Hz is converted by a multiplier so that the signal has a frequency of “n” times so as to use the clock signal for triggering a flip-flop the operation frequency of which is f1 b/s in the synchronous digital circuit. The multiplier is arranged in the vicinity of the flip-flop triggered by the clock signal of f1 Hz so as to avoid the effect of the deterioration of the operation frequency by interconnect capacitance. The maximum operation frequency of the transceiver circuit determined based upon the operating frequency of the synchronous digital circuit can be enhanced up to the maximum operation frequency of the flip-flop.

Abstract: A write driver circuit capable of controlling the waveform of overshoot of a write current, more specifically, controlling a rise, amplitude, and duration of overshoot (OS) in the waveform of an output current independently of one another. The write driver circuit includes transistors for controlling the rise, amplitude, and duration of OS, an impedance matching unit between the write driver and the load, and a canceller of reflection waves from the head.

Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.

Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced.

Abstract: The invention provides a transceiver circuit for communication that enhances the operation frequency of a synchronous digital circuit up to the maximum frequency of a flip-flop and inhibits the occurrence of jitters.

Abstract: A semiconductor integrated circuit device includes a first variable delay circuit which delays a timing signal for activating a sense amplifier which is supplied with a signal read out from a memory array and amplifies the signal so that a timing difference between a dummy signal read out from a dummy memory cell and the timing signal of the sense amplifier is detected by a detection circuit to be made small in accordance with an output of the detection circuit, and a second variable delay circuit which adjusts a relative timing difference between the dummy signal and the timing signal of the sense amplifier.

Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. According to the present invention, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and in a semiconductor memory for example, the reduction of access time and power consumption and the increase of the cycles are enabled.

Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced.

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic is configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to a potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.

Abstract: A semiconductor integrated circuit device includes a first variable delay circuit which delays a timing signal for activating a sense amplifier which is supplied with a signal read out from a memory array and amplifies the signal so that a timing difference between a dummy signal read out from a dummy memory cell and the timing signal of the sense amplifier is detected by a detection circuit to be made small in accordance with an output of the detection circuit, and a second variable delay circuit which adjusts a relative timing difference between the dummy signal and the timing signal of the sense amplifier.

Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.