Patents by Inventor Takeshi Morita

Takeshi Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180110757
    Abstract: The present disclosure provides compositions and methods for treating pruritis and for treating certain types of pain.
    Type: Application
    Filed: October 19, 2017
    Publication date: April 26, 2018
    Inventors: Diana M. Bautista, Takeshi Morita, Rose Zabel Hill, Rachel B. Brem
  • Publication number: 20170287898
    Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.
    Type: Application
    Filed: March 27, 2017
    Publication date: October 5, 2017
    Inventors: Takeshi MORITA, Kazuhiro TSUMURA
  • Publication number: 20170271453
    Abstract: Provided is a semiconductor device including a second conductivity type low-concentration diffusion layer (101) for an electric field relaxation reaching a lower portion of a gate oxide film so as to cover a drain diffusion layer (107), in which a second conductivity type medium-concentration diffusion layer (102) is formed within the second conductivity type low-concentration diffusion layer (101) for the electric field relaxation, and a second conductivity type high-concentration diffusion layer (103), which has a high concentration and small variation in structure due to suppression of heat treatment as much as possible, is formed within the second conductivity type medium-concentration diffusion layer (102).
    Type: Application
    Filed: March 15, 2017
    Publication date: September 21, 2017
    Inventors: Keisuke NAGAO, Takeshi MORITA
  • Publication number: 20170221514
    Abstract: In a tape recording medium, a sliding layer has an electric resistance of 1×108 ?/sq or less, and contains carbon particles and solid particles. The carbon particles have a primary particle size of 30 nm or less and a BET specific surface area of 100 m2/g or more. The solid particles have a primary particle size of 100 nm or less, a Mohs' hardness in a range from 2.5 to 8, inclusive, a density of 3 g/cm3 or more, and a BET specific surface area of 30 m2/g or more.
    Type: Application
    Filed: October 13, 2016
    Publication date: August 3, 2017
    Inventors: KENYA HORI, TAKESHI MORITA, HIROYUKI OTA, TATSUMASA YAMADA
  • Patent number: 9627315
    Abstract: A semiconductor device includes a semiconductor substrate, and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another. Each interconnection layer includes a real interconnection and a dummy interconnection covered with an insulative film. The interconnection layers include a first interconnection layer including a first real interconnection, a second interconnection layer stacked on the first interconnection layer and including an overlapping dummy interconnection that overlaps the first real interconnection in a stacking direction of the plurality of interconnection layers in a sectional view, and a third interconnection layer stacked on the second interconnection layer and including a second real interconnection that overlaps the overlapping dummy interconnection in the stacking direction of the plurality of interconnection layers in the sectional view.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: April 18, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Takeshi Morita
  • Patent number: 9618802
    Abstract: According to one embodiment, an apparatus for manufacturing a display device, includes: a first holding section configured to hold a first substrate; a second holding section configured to hold a second substrate; a turning section configured to turn the first holding section such that the first substrate and the second substrate face each other; an elevation unit configured to elevate the second holding section and attach the first substrate and the second substrate via an adhesive layer; and a first radiation section configured to radiate ultraviolet rays from at least one direction of an inclined lower side of an opening of a space between the first substrate and the second substrate and an inclined upper side of the opening toward the opening.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Matsuura, Akira Ushijima, Kentaro Miyazaki, Takeshi Toyoshima, Takahide Miyahara, Takeshi Morita
  • Publication number: 20170033041
    Abstract: A semiconductor device includes a semiconductor substrate, and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another. Each interconnection layer includes a real interconnection and a dummy interconnection covered with an insulative film. The interconnection layers include a first interconnection layer including a first real interconnection, a second interconnection layer stacked on the first interconnection layer and including an overlapping dummy interconnection that overlaps the first real interconnection in a stacking direction of the plurality of interconnection layers in a sectional view, and a third interconnection layer stacked on the second interconnection layer and including a second real interconnection that overlaps the overlapping dummy interconnection in the stacking direction of the plurality of interconnection layers in the sectional view.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 2, 2017
    Applicant: ROHM CO., LTD.
    Inventor: Takeshi MORITA
  • Publication number: 20160272059
    Abstract: An input shaft (1) connectable to an engine (5), an output gear (2), a transmission case (3) and a Ravigneaux planetary gear unit (4) are provided. Four rotational elements of the Ravigneaux planetary gear unit (4) are a single pinion side sun gear (Ss), a carrier (C), a ring gear (R) and a double pinion side sun gear (Sd) which are arranged orderly on a common speed diagram. The single pinion side sun gear (Ss) is constantly connected to a motor/generator (6), and the ring gear (R) is constantly connected to the output gear (2). And, with usage of a low & reverse clutch (L&R/C), a high clutch (H/C) and a low brake (L/B), a first speed (1st), a second speed (2nd), a third speed (3rd) and a stepless change speed (eCVT) are established.
    Type: Application
    Filed: October 28, 2014
    Publication date: September 22, 2016
    Applicant: JATCO Ltd
    Inventors: Kenichi WATANABE, Takeshi MORITA
  • Patent number: 9390743
    Abstract: Provided is an optically recordable or reproducible tape recording medium including tracking pattern groups and non-tracking pattern areas. The tracking pattern groups are repeatedly provided along a longitudinal direction of the tape, and each of the groups includes a plurality of tracking patterns. The non-tracking pattern areas are respectively provided between the tracking patterns. In addition, the non-tracking pattern areas have different lengths along the longitudinal direction of the tape.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: July 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akinaga Natsui, Takeshi Morita
  • Patent number: 9280997
    Abstract: Provided is a tape recording medium including: a base layer having a first surface and a second surface; a first recording layer disposed over the first surface of the base layer and capable of optically recording first data; an imprinted layer disposed between the base layer and the first recording layer; and a second recording layer. The second recording layer is disposed over the second surface of the base layer, contains a magnetic material, and has recorded second data different from the first data.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: March 8, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akinaga Natsui, Takeshi Morita
  • Patent number: 9154055
    Abstract: Disclosed is a drive device 1 which is adapted to move a driven member used on a speed difference between during extending and during contracting in a course of vibration of a vibrator. The vibrator, e.g., a piezoelectric element 4, 5, is formed in a structure which has two resonance modes identical in terms of a vibration direction, and allows a ratio between resonance frequencies of the two resonance modes to become approximately 2. A drive signal to be given to the vibrator is configured to approximately conform to the two resonance modes. The drive device 1 having the above configuration makes it possible to generate pseudo-sawtooth displacement vibration multiplied by an amplitude amplification factor Q through resonance, thereby improving a movement speed, and allow a larger part of input energy to be used for mechanical vibration, thereby improving energy efficiency.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: October 6, 2015
    Assignee: KONICA MINOLTA, INC.
    Inventors: Takeshi Morita, Ryuichi Yoshida
  • Publication number: 20150255107
    Abstract: Provided is an optically recordable or reproducible tape recording medium including tracking pattern groups and non-tracking pattern areas. The tracking pattern groups are repeatedly provided along a longitudinal direction of the tape, and each of the groups includes a plurality of tracking patterns. The non-tracking pattern areas are respectively provided between the tracking patterns. In addition, the non-tracking pattern areas have different lengths along the longitudinal direction of the tape.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 10, 2015
    Inventors: Akinaga NATSUI, Takeshi MORITA
  • Publication number: 20150255104
    Abstract: Provided is a tape recording medium including: a base layer having a first surface and a second surface; a first recording layer disposed over the first surface of the base layer and capable of optically recording first data; an imprinted layer disposed between the base layer and the first recording layer; and a second recording layer. The second recording layer is disposed over the second surface of the base layer, contains a magnetic material, and has recorded second data different from the first data.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 10, 2015
    Inventors: Akinaga NATSUI, Takeshi MORITA
  • Patent number: 9123779
    Abstract: A semiconductor device having a multi-level interconnection structure including a plurality of interconnection layers stacked one on another on a semiconductor substrate is provided, and a production method for the semiconductor device. In the production method, forming each of the interconnection layers of the multi-level interconnection structure includes: forming a real interconnection and a dummy interconnection, forming an insulative film covering the real interconnection and the dummy interconnection, and planarizing a surface of the insulative film. The production method may include computing an in-plane distribution of an overall thickness of the multi-level interconnection structure to be expected when no dummy interconnection is formed; and defining a dummy present zone and a dummy absent zone. The dummy interconnection is formed in the defined dummy present zone outside the defined dummy absent zone in each of the interconnection layers.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: September 1, 2015
    Assignee: ROHM CO., LTD.
    Inventor: Takeshi Morita
  • Publication number: 20140353845
    Abstract: A production method for a semiconductor device having a multi-level interconnection structure including a plurality of interconnection layers stacked one on another on a semiconductor substrate is provided. In the production method, the step of forming each of the interconnection layers of the multi-level interconnection structure includes an interconnection forming step of forming a real interconnection and a dummy interconnection, an insulative film forming step of forming an insulative film covering the real interconnection and the dummy interconnection, and a planarization step of planarizing a surface of the insulative film. The production method includes: a step of computing an in-plane distribution of an overall thickness of the multi-level interconnection structure to be expected when no dummy interconnection is formed; and a step of defining a dummy present zone and a dummy absent zone.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 4, 2014
    Applicant: ROHM CO., LTD.
    Inventor: Takeshi MORITA
  • Publication number: 20140284452
    Abstract: According to one embodiment, an apparatus for manufacturing a display device, includes: a first holding section configured to hold a first substrate; a second holding section configured to hold a second substrate; a turning section configured to turn the first holding section such that the first substrate and the second substrate face each other; an elevation unit configured to elevate the second holding section and attach the first substrate and the second substrate via an adhesive layer; and a first radiation section configured to radiate ultraviolet rays from at least one direction of an inclined lower side of an opening of a space between the first substrate and the second substrate and an inclined upper side of the opening toward the opening.
    Type: Application
    Filed: September 16, 2013
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi MATSUURA, Akira Ushijima, Kentaro Miyazaki, Takeshi Toyoshima, Takahide Miyahara, Takeshi Morita
  • Publication number: 20140283366
    Abstract: According to one embodiment, an apparatus for manufacturing a display device, includes: a first holding section configured to hold a first substrate; a second holding section configured to hold a second substrate; a turning section configured to turn the first holding section such that the first substrate and the second substrate face each other; a support section configured to support the first holding section after the turning; an adjustment section; and an elevation section. The adjustment section is provided at an upper end of the support section and is configured to adjust a distance between the first holding section after the turning and the upper end of the support section. The elevation section is configured to elevate the second holding section and attach the first substrate and the second substrate via an adhesive layer.
    Type: Application
    Filed: September 16, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takahide MIYAHARA, Takeshi Morita, Kentaro Miyazaki
  • Patent number: 8591104
    Abstract: A temperature sensor having a weld zone between an element electrode wire and a sheath core wire. When a section of the weld zone is taken orthogonally to the axial direction and in such a manner as to pass through a center point, L/D is greater or equal to 0.6, wherein D represents the diameter of the element electrode wire, and L represents the length of a chord connecting a first weld point and a second weld point as defined herein.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: November 26, 2013
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Tatsuya Suzuki, Go Hanzawa, Takeshi Morita, Akihiro Fukata, Ken Masuda
  • Patent number: 8512202
    Abstract: A shift controller controls a transmission for a hybrid vehicle in which: an engine and a motor are connected together via a clutch; and the transmission is placed between the motor and driving wheels. The shift controller has: a first shift controlling unit which performs shift control on a basis of at least one of transmission efficiency of the transmission and power generation efficiency of the motor in a case where regeneration is performed with the clutch disengaged during deceleration of the hybrid vehicle; and a second shift controlling unit which performs shift control to make a transmission gear ratio of the transmission smaller than in the shift control performed by the first shift controlling unit in a case where the regeneration is performed with the clutch engaged during the deceleration of the hybrid vehicle.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: August 20, 2013
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Yoshikazu Oota, Ryozo Hiraku, Takeshi Morita, Akira Takano
  • Patent number: 8446535
    Abstract: A method of manufacturing a three dimensional image display device includes bonding a lens plate having a lenticular lens to a display panel configured to display an image, with a partially-discontinuous frame-shaped adhesive member interposed in between while having the lenticular lens facing the display panel. The method also includes depressurizing a hermetic inner space formed by the display panel, the adhesive member, and the lens plate, and sealing an opening section communicating with the inner space.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: May 21, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Miyazaki, Takashi Miyauchi, Takeshi Morita