Patents by Inventor Takeshi Nagai
Takeshi Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7669108Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.Type: GrantFiled: June 28, 2007Date of Patent: February 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Publication number: 20100039276Abstract: A portable electronics includes detection unit which detects a state of the portable electronics, storage unit which stores a detection result of the detection unit at a first period, and determination unit which reads out, every time a second period longer than the first period has elapsed, a plurality of detection results stored in the storage unit during the second period and determines the state of the portable electronics based on the plurality of readout detection results.Type: ApplicationFiled: July 23, 2009Publication date: February 18, 2010Inventor: Takeshi Nagai
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Patent number: 7610542Abstract: A synchronous semiconductor memory which performs a pipeline operation includes an error correction circuit, an output circuit, and first and second write circuits. The first write circuit is configured to overwrite at least a portion of externally input write data on data read out from a memory cell and corrected by the error correction circuit, and write the overwritten data in the memory cell. The output circuit is configured to output the overwritten data outside a chip. The second write circuit is configured to reoverwrite at least a portion of write data which is externally input at a different time on the overwritten data, encode the reoverwritten data, and write the encoded data in the memory cell.Type: GrantFiled: June 16, 2006Date of Patent: October 27, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Nagai
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Patent number: 7583846Abstract: A texture image compressing device includes a separating unit configured to separate intensity maps that include intensity values and light source-independent texture images, those images including color components from a plurality of texture images corresponding to a plurality of different light source directions and a plurality of different viewpoint directions.Type: GrantFiled: April 2, 2008Date of Patent: September 1, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yasunobu Yamauchi, Shingo Yanagawa, Masahiro Sekine, Takeshi Nagai, Hideyuki Ueno, Nakaba Kogure
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Patent number: 7525871Abstract: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse data is long, there is a possibility that a value of the fuse data may be inverted due to an influence of noises. Thus, a decoder is arranged in the transfer path of the fuse data, and encoded data is stored in the fuse elements. By performing error detection/correction in the decoder, the high reliability is assured with respect to chip operations and the like.Type: GrantFiled: April 23, 2007Date of Patent: April 28, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Nagai, Ryo Haga
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Patent number: 7506221Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.Type: GrantFiled: May 5, 2006Date of Patent: March 17, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7502975Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.Type: GrantFiled: May 30, 2007Date of Patent: March 10, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Nagai, Yoshihiro Kikuchi, Tadaaki Masuda
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Patent number: 7500159Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.Type: GrantFiled: May 30, 2007Date of Patent: March 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Nagai, Yoshihiro Kikuchi, Tadaaki Masuda
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Patent number: 7496807Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.Type: GrantFiled: May 30, 2007Date of Patent: February 24, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Nagai, Yoshihiro Kikuchi, Tadaaki Masuda
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Patent number: 7487410Abstract: Methods and systems are provided for decoding. In one exemplary embodiment, the method may include detecting a synchronization code at a position selected from a plurality of synchronization code inserting positions. The plurality of synchronization code inserting positions may be positioned at periodic intervals in an input code string, and the input code string may include a multiplexed code string and information indicative of a delimiter of the multiplexed code string. The information may be arranged just after the multiplexed code string or between the multiplexed code string and a subsequent synchronization code. The method may also include demultiplexing the input code string on the basis of the position of the synchronization code detected by the detecting, to produce kinds of compressed codes. The method may further include decoding the compressed codes to output a reconstructed signal, each of the kinds of compressed codes being a variable length code.Type: GrantFiled: May 12, 2005Date of Patent: February 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7475298Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.Type: GrantFiled: October 23, 2006Date of Patent: January 6, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7472317Abstract: In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.Type: GrantFiled: October 23, 2006Date of Patent: December 30, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7472316Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.Type: GrantFiled: October 23, 2006Date of Patent: December 30, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7469364Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check-bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.Type: GrantFiled: May 5, 2006Date of Patent: December 23, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7464320Abstract: A semiconductor memory device has a memory cell array in which a plurality of memory cells are arranged and operates in sync with a clock signal. A read and write operations are performed in the same cycle of the clock signal. The read operation allows the read column selection lines that have been designated by a first column address to connect the read data bus to the bit lines. The write operation allows the write column selection lines that have been designated by a second column address to connect the write data bus to the bit lines. Further, in the write operation, the data obtained by combining the data that has been error-corrected by the syndrome generation circuit and correction circuit with the data that has been input to the input circuit is coded by the code generation circuit and written in the memory cells.Type: GrantFiled: November 16, 2005Date of Patent: December 9, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Nagai, Shinji Miyano
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Patent number: 7464305Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.Type: GrantFiled: June 28, 2007Date of Patent: December 9, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7464304Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.Type: GrantFiled: October 23, 2006Date of Patent: December 9, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7457994Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.Type: GrantFiled: May 5, 2006Date of Patent: November 25, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7454669Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting-/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.Type: GrantFiled: October 23, 2006Date of Patent: November 18, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
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Patent number: 7447949Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string , for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.Type: GrantFiled: October 23, 2006Date of Patent: November 4, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai