Abstract: A pulse signal generation device including a reference signal cycle measuring unit for receiving input of a reference signal to calculate a cycle of the reference signal by using an appropriate clock signal, a pulse width calculation unit for obtaining the number of pulses oscillating during a period of one cycle of a reference signal and dividing a cycle of a reference signal on a clock signal basis measured by the reference signal cycle measuring unit by the number of pulses of the pulse signal to calculate a pulse width of a pulse signal on the basis of the clock signal, and a pulse signal generation unit for generating a pulse signal with a pulse width calculated by the pulse width calculation unit.

Abstract: It is intended to shorten the read time after receiving a read command. The method comprises step S2 for determining whether or not a read request address for a new read command is identical to an address being currently read, step S4 for, if they are identical, outputting CD-ROM stored data RD held in a memory as read data against the read command after completion of the current read process, and step S6 for, if they are not identical, performing a seek operation, performing a read process after completion of the seek operation, and outputting the read data after completion of the read process.

Abstract: A data memory system comprising a memory including a plurality of memory locations from which a stored data is readable and to which data is writable, an address latch for receiving and holding from an external device a relative address designating a memory location to be accessed, and an address decoder for designating an absolute address of a memory location of the plurality of memory locations on the basis of the relative address held in the address latch. This designated memory location is called an "m"th memory location. An address translation unit is controlled to change the "m"th memory location designated by the relative address to an "n"th memory location which is different from the "m"th memory location, where "m" and "n" are positive integers, based on the number of writes to the memory and the existence of coincident data in the "m"th and "n"th memory locations.