Patents by Inventor Takeshi Onogami

Takeshi Onogami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879144
    Abstract: A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kengo Aoya, Masamitsu Matsuura, Takeshi Onogami, Hideaki Matsunaga
  • Publication number: 20200058570
    Abstract: A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 20, 2020
    Inventors: Kengo Aoya, Masamitsu Matsuura, Takeshi Onogami, Hideaki Matsunaga
  • Publication number: 20160240392
    Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Anindya Poddar, Mark Allen Gerber, Mutsumi Masumoto, Masamitsu Matsuura, Kengo Aoya, Takeshi Onogami
  • Publication number: 20150147845
    Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 28, 2015
    Inventors: Anindya Poddar, Mark Allen Gerber, Mutsumi Masumoto, Masamitsu Matsuura, Kengo Aoya, Takeshi Onogami
  • Publication number: 20150008566
    Abstract: A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape (292); attaching semiconductor chips—coated with a polymer layer having windows for chip terminals —face-down onto the tape (293); laminating low CTE insulating material to fill gaps between chips and grid (294); turning over assembly to place carrier under backside of chips and lamination and to remove tape (295); plasma-cleaning assembly front side, sputtering uniform metal layer across assembly (296); optionally plating metal layer (297); and patterning sputtered layer to form rerouting traces and extended contact pads for assembly (298).
    Type: Application
    Filed: July 1, 2014
    Publication date: January 8, 2015
    Inventors: Mark A. Gerber, Mutsumi Masumoto, Kenji Masumoto, Anindya Poddar, Kengo Aoya, Masamitsu Matsuura, Takeshi Onogami