Abstract: A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.

Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

Abstract: The present invention relates to kits and methods for determining (diagnosing) prostate cancer malignancy and to predict patient prognoses. In addition to the Gleason's classification and the TMN classification, the invention kit and methods provide improved procedures with molecular markers. These new diagnostic methods provide methods capable of determining prostate cancer malignancy more accurately and easily through combination with the Gleason's classification via biopsies at an early stage before surgical operation; even when specimens taken through a fine needle examination are used instead of specimens extracted during a surgical operation.

Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.

Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.

Abstract: A semiconductor device employs a SESO memory or a phase change memory which has a smaller memory cell area than SRAM. The semiconductor device has a plurality of memory banks each composed of the SESO or phase change memories, and a cache memory which has a number of ways equal to the ratio of a write speed (m) to a read speed (n). The semiconductor device controls the cache memory such that a write back operation is not repeated on the same memory bank.

Abstract: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 ?m, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

Abstract: In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.

Abstract: There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

Abstract: In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.

Abstract: Provided are a wire electric discharge machining method for poorly conductive materials, such as solar cell silicon, and a semiconductor wafer manufacturing method and a solar battery cell manufacturing method based on the wire electric discharge machining method. Electrical discharge machining of a high volume resistivity, hard and brittle materials, having a volume resistivity that is equal to or higher than 0.5 ?·cm and equal to or lower than 5 ?·cm is performed by applying a pulse voltage having a pulse width that is equal to or higher than 1 ?sec and equal to or lower than 4 ?sec and having a peak current at the time of machining a wire electrode that is equal to or higher than 10A and equal to or lower than 50A to a wire electrode and generating a discharge pulse between the wire electrode and a subject to be machined.

Abstract: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

Abstract: A phase change memory is provided with a write data register, an output data selector, a write address register, an address comparator and a flag register. Write data is not only written into a memory cell but also retained by the write data register until the next write cycle. If a read access occurs to that address before the next write cycle, data is read out from the register without reading the data from the memory cell array. Without elongating the cycle time, it is possible not only to use a long time to write data into a memory cell therein but also to make longer the interval between the time when a write operation is done and the time when the subsequent read operation is made from that memory cell. As a result, data can be written reliably.

Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

Abstract: There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.