Abstract: A starter for cranking an internal combustion engine is mainly composed of an electric motor and a magnetic switch having a battery bolt connected to an on-board battery and a motor bolt connected to the electric motor. When the magnetic switch is closed, electric power is supplied to the electric motor to thereby generate a rotational torque for cranking the engine. One end of a motor terminal is electrically connected to the motor bolt, and the other end is led into a motor casing through a rubber insulator supported on the motor casing. The motor terminal includes one or more curved portions having resiliency, and they are positioned between the rubber insulator and the motor bolt. Water penetration into the motor casing is prevented by the rubber insulator, and the vibration of the motor terminal is alleviated by resiliency of the curved portions.

Abstract: Intermediate data ai, bi, ci, and di are prepared by an intermediate data preparing equipment 4 from a cryptographic key through a nonlinear type function operation and the like, an extended key preparing equipment 5 selects a [Xr], b [Yr], c [Zr], and d [Wr] corresponding to the number of stages r from the intermediate data, and rearranges the data as well as conducts that of bit operation to prepare extended keys, whereby an extended key preparing apparatus by which an extended key required in the case where common key cryptosystem is applied can be safely prepared at a high speed, a process for preparing such an extended key, and a recording medium used therefor are provided.

Abstract: A motor includes a stator section with a two-phase structure having first and second stator assemblies disposed in an axial direction, and a plurality of pole teeth arranged at an electrical angle of 90 degrees along inner circumferences of the first and second stator assemblies, and a rotor section including a rotation shaft, and first and second permanent magnets that are disposed opposite to and spaced a predetermined gap from the pole teeth and affixed to the rotation shaft with a gap provided between the first and second permanent magnets in the axial direction. Each of the first and second permanent magnets has an effective section at an outer circumference thereof that has multiple poles alternately magnetized with N poles and S poles, and has a protruded section that has a diameter smaller than an outer diameter of the effective section and protrudes in the axial direction.

Abstract: A starter for cranking an internal combustion engine is mainly composed of an electric motor and a magnetic switch having a battery bolt connected to an on-board battery and a motor bolt connected to the electric motor. When the magnetic switch is closed, electric power is supplied to the electric motor to thereby generate a rotational torque for cranking the engine. One end of a motor terminal is electrically connected to the motor bolt, and the other end is led into a motor casing through a rubber insulator supported on the motor casing. The motor terminal includes one or more curved portions having resiliency, and they are positioned between the rubber insulator and the motor bolt. Water penetration into the motor casing is prevented by the rubber insulator, and the vibration of the motor terminal is alleviated by resiliency of the curved portions.

Abstract: A self refresh timing generator detects the presence/absence of a read signal output by a control signal generator employed in a DRAM controller to a memory bank and, if no read signal is detected in a predetermined period of time, a refresh signal is generated and output to a refresh suppression register, which has been set in on or off status by the control signal generator in advance. If the refresh suppression register has been set in on status, the refresh signal is blocked and thus not output to the memory bank in the DRAM. If the refresh suppression register has been set in set in off status, on the other hand, the refresh suppression register passes on the refresh signal to the predetermined page of the memory bank associated with the refresh suppression register. As a result, the power consumption of the DRAM is reduced and a high speed read operation can be implemented with a high degree of probability.

Abstract: A self refresh timing generator detects the presence/absence of a read signal output by a control signal generator employed in a DRAM controller to a memory bank and, if no read signal is detected in a predetermined period of time, a refresh signal is generated and output to a refresh suppression register, which has been set in on or off status by the control signal generator in advance. If the refresh suppression register has been set in on status, the refresh signal is blocked and thus not output to the memory bank in the DRAM. If the refresh suppression register has been set in set in off status, on the other hand, the refresh suppression register passes on the refresh signal to the predetermined page of the memory bank associated with the refresh suppression register. As a result, the power consumption of the DRAM is reduced and a high speed read operation can be implemented with a high degree of probability.

Abstract: A self refresh timing generator detects the presence/absence of a read signal output by a control signal generator employed in a DRAM controller to a memory bank and, if no read signal is detected in a predetermined period of time, a refresh signal is generated and output to a refresh suppression register, which has been set in on or off status by the control signal generator in advance. If the refresh suppression register has been set in on status, the refresh signal is blocked and thus not output to the memory bank in the DRAM. If the refresh suppression register has been set in set in off status, on the other hand, the refresh suppression register passes on the refresh signal to the predetermined page of the memory bank associated with the refresh suppression register. As a result, the power consumption of the DRAM is reduced and a high speed read operation can be implemented with a high degree of probability.

Abstract: A self refresh timing generator detects the presence/absence of a read signal output by a control signal generator employed in a DRAM controller to a memory bank and, if no read signal is detected in a predetermined period of time, a refresh signal is generated and output to a refresh suppression register, which has been set in on or off status by the control signal generator in advance. If the refresh suppression register has been set in on status, the refresh signal is blocked and thus not output to the memory bank in the DRAM. If the refresh suppression register has been set in set in off status, on the other hand, the refresh suppression register passes on the refresh signal to the predetermined page of the memory bank associated with the refresh suppression register. As a result, the power consumption of the DRAM is reduced and a high speed read operation can be implemented with a high degree of probability.

Abstract: By providing a unit receiving the input of a set T of bit numbers that are obtained by unequally dividing all the bit numbers of input data to be given to a computing apparatus, a unit outputting a value AT indicating an existence probability of an appropriate linear converting unit corresponding to a plurality of S boxes of which the input and output bit numbers are equivalent to the divided bit numbers, a unit determining that an appropriate linear converting unit is present when the value of AT is positive, and a unit forming a pseudo MDS matrix as the linear converting unit, computation is executed using a unit with an excellent data diffusion performance as the linear converting unit in SPN structure, when the input number is not the same as the output number among a plurality of S boxes of the SPN structure in an F function.

Abstract: Intermediate data ai, bi, ci, and di are prepared by an intermediate data preparing equipment 4 from a cryptographic key through a nonlinear type function operation and the like, an extended key preparing equipment 5 selects a [Xr], b [Yr], c [Zr], and d [Wr] corresponding to the number of stages r from the intermediate data, and rearranges the data as well as conducts that of bit operation to prepare extended keys, whereby an extended key preparing apparatus by which an extended key required in the case where common key cryptosystem is applied can be safely prepared at a high speed, a process for preparing such an extended key, and a recording medium used therefor are provided.

Abstract: An optimization processing unit optimizes an input and output bit number of an S-box based on parameters inputted from an input unit. The examples of the parameters are memory capacity of a primary cache memory, entire input and output bit number, and smallest input and output number of the S-box. An S-box generating unit generates an S-box in accordance with the optimized input and output bit number of the S-box. Then, an F-function generating unit generates an F-function by aligning a plurality of S-boxes thus generated.