Patents by Inventor Takeshi Uenoyama
Takeshi Uenoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210296528Abstract: Provided is a display device including a light emitting unit that can emit a plurality of types of light having different wavelengths to the outside at a desired ratio with high intensity without increasing manufacturing costs in proportion to a number of pixels even when the number of pixels increases. Provided is a display device including a light emitting unit in which a plurality of types of PiN junction-type light emitting diodes that emit light having different wavelengths are arranged on the same substrate, and at least one type among the plurality of types of light emitting diodes has an active layer containing a rare earth element. Provided is a display device in which a plurality of types of light emitting diodes are sequentially stacked on the surface of a substrate, and a light emitting layer for one color is formed to overlap at least a portion of a light emitting layer for another color.Type: ApplicationFiled: June 9, 2021Publication date: September 23, 2021Applicant: OSAKA UNIVERSITYInventors: Yasufumi FUJIWARA, Takeshi UENOYAMA, Jun TATEBAYASHI, Shuhei ICHIKAWA
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Publication number: 20090159924Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: ApplicationFiled: February 24, 2009Publication date: June 25, 2009Applicant: Panasonic CorporationInventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
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Patent number: 7368766Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: GrantFiled: July 15, 2004Date of Patent: May 6, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
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Publication number: 20070228395Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: ApplicationFiled: June 7, 2007Publication date: October 4, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
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Patent number: 6989553Abstract: An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.Type: GrantFiled: July 23, 2003Date of Patent: January 24, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Osamu Kusumoto, Makoto Kitabatake, Takeshi Uenoyama
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Patent number: 6864507Abstract: P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.Type: GrantFiled: June 12, 2003Date of Patent: March 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiya Yokogawa, Makoto Kitabatake, Osamu Kusumoto, Kunimasa Takahashi, Takeshi Uenoyama
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Patent number: 6861672Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: GrantFiled: November 6, 2001Date of Patent: March 1, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
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Publication number: 20050003571Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: ApplicationFiled: July 15, 2004Publication date: January 6, 2005Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
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Publication number: 20040217375Abstract: An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.Type: ApplicationFiled: July 23, 2003Publication date: November 4, 2004Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Osamu Kusumoto, Makoto Kitabatake, Takeshi Uenoyama
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Patent number: 6690035Abstract: An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.Type: GrantFiled: November 1, 2001Date of Patent: February 10, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Osamu Kusumoto, Makoto Kitabatake, Takeshi Uenoyama
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Patent number: 6674100Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.Type: GrantFiled: April 5, 2002Date of Patent: January 6, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Minoru Kubo, Katsuya Nozawa, Masakatsu Suzuki, Takeshi Uenoyama, Yasuhito Kumabuchi
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Patent number: 6674131Abstract: In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.Type: GrantFiled: February 26, 2002Date of Patent: January 6, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Makoto Kitabatake, Osamu Kusumoto, Takeshi Uenoyama, Koji Miyazaki
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Publication number: 20030227061Abstract: P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.Type: ApplicationFiled: June 12, 2003Publication date: December 11, 2003Inventors: Toshiya Yokogawa, Makoto Kitabatake, Osamu Kusumoto, Kunimasa Takahashi, Takeshi Uenoyama
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Patent number: 6624462Abstract: A Pt/Ti film is formed on a substrate, and the Pt/Ti film is patterned in to a bottom electrode. Subsequently, a SrTiO3film, that is, a dielectric film, is formed on the substrate by sputtering using a mixture of an Ar gas, an O2 gas and a N2 gas as a film forming gas. The SrTiO3 film is patterned into a capacitor dielectric film formed on the bottom electrode. A top electrode is then formed on the capacitor dielectric film. Since a N2 gas is used as the film forming gas in addition to an Ar/O2 gas, a SrTiO3 film with a high dielectric constant and small leakage can be formed at a low temperature. By using this SrTiO3 film, a thin film capacitor with high capacitance and good dielectric characteristics can be obtained.Type: GrantFiled: August 17, 2000Date of Patent: September 23, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Naoki Kohara, Taisuke Sawada, Masatoshi Kitagawa, Takeshi Uenoyama
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Patent number: 6617653Abstract: P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.Type: GrantFiled: January 30, 2002Date of Patent: September 9, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiya Yokogawa, Makoto Kitabatake, Osamu Kusumoto, Kunimasa Takahashi, Takeshi Uenoyama
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Patent number: 6566692Abstract: An n-GaN layer is provided as an emitter layer for supplying electrons. A non-doped (intrinsic) AlxGa1−xN layer (0≦x≦1) having a compositionally graded Al content ratio x is provided as an electron transfer layer for transferring electrons toward the surface. A non-doped AlN layer having a negative electron affinity (NEA) is provided as a surface layer. Above the AlN layer, a control electrode and a collecting electrode are provided. An insulating layer formed of a material having a larger electron affinity than that of the AlN layer is interposed between the control electrode and the collecting electrode. This provides a junction transistor which allows electrons injected from the AlN layer to conduct through the conduction band of the insulating layer and then reach the collecting electrode.Type: GrantFiled: August 8, 2001Date of Patent: May 20, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Uenoyama, Masahiro Deguchi
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Publication number: 20030006415Abstract: In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.Type: ApplicationFiled: February 26, 2002Publication date: January 9, 2003Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Makoto Kitabatake, Osamu Kusumoto, Takeshi Uenoyama, Koji Miyazaki
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Publication number: 20020105015Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.Type: ApplicationFiled: April 5, 2002Publication date: August 8, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Minoru Kubo, Katsuya Nozawa, Masakatsu Suzuki, Takeshi Uenoyama, Yasuhito Kumabuchi
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Patent number: 6399970Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.Type: GrantFiled: September 16, 1997Date of Patent: June 4, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Minoru Kubo, Katsuya Nozawa, Masakatsu Suzuki, Takeshi Uenoyama, Yasuhito Kumabuchi
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Publication number: 20020054616Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: ApplicationFiled: November 6, 2001Publication date: May 9, 2002Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi