Patents by Inventor Takeshi Yamato
Takeshi Yamato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8092696Abstract: An insulating layer made of an insulator film or the like is prepared. Then, a thin metal film and a thin copper film are formed in sequence on the insulating layer. The thin copper film is subsequently laminated with a dry film or the like, and exposed and developed to form a plating resist thereon that have patterns opposite to conductor patterns which are formed in a subsequent step. This is followed by forming conductor patterns made of copper, by electrolytic plating using an electrolytic copper sulfate plating solution, on the surfaces of the thin copper film where the plating resist is not formed. The plating resist is then removed by, for example, stripping. After this, the thin copper film is held at a temperature of not less than 200° C. and not more than 300° C. for approximately an hour to be thermally treated. Then, the thin copper film and the thin metal film are removed by chemical etching except the portions under the conductor patterns.Type: GrantFiled: December 13, 2007Date of Patent: January 10, 2012Assignee: Nitto Denko CorporationInventors: Kei Nakamura, Takeshi Yamato
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Publication number: 20080164236Abstract: An insulating layer made of an insulator film or the like is prepared. Then, a thin metal film and a thin copper film are formed in sequence on the insulating layer. The thin copper film is subsequently laminated with a dry film or the like, and exposed and developed to form a plating resist thereon that have patterns opposite to conductor patterns which are formed in a subsequent step. This is followed by forming conductor patterns made of copper, by electrolytic plating using an electrolytic copper sulfate plating solution, on the surfaces of the thin copper film where the plating resist is not formed. The plating resist is then removed by, for example, stripping. After this, the thin copper film is held at a temperature of not less than 200° C. and not more than 300° C. for approximately an hour to be thermally treated. Then, the thin copper film and the thin metal film are removed by chemical etching except the portions under the conductor patterns.Type: ApplicationFiled: December 13, 2007Publication date: July 10, 2008Applicant: NITTO DENKO CORPORATIONInventors: Kei NAKAMURA, Takeshi YAMATO
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Patent number: 7323093Abstract: A producing method of a flexible wired circuit board that can prevent the formation of a gap between an elongate substrate and a stiffener sheet bonded thereto to prevent contamination of the flexible wired circuit board obtained. In the process subsequent to the process of forming a conductive pattern 3 on a surface of the elongate substrate 1 by the semi-additive process using electrolysis plating and then annealing the elongate substrate 1 with the conductive pattern 3 in its wound up state, a stiffener sheet 9 having a width narrower than the elongate substrate 1 is bonded to the back side of the elongate substrate 1. Thereafter, an oxidized film formed on a surface of the conductive pattern 3 is removed and then a solder resist 11 is formed thereon. This prevents the strip of the stiffener sheet 9 from the elongate substrate 1 and in turn prevents etching solution or developing solution from entraining in a gap therebetween.Type: GrantFiled: September 28, 2004Date of Patent: January 29, 2008Assignee: Nitto Denko CorporationInventors: Toshiki Naito, Yoshifumi Shinogi, Takeshi Yamato
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Publication number: 20060000637Abstract: An insulating layer made of an insulator film or the like is prepared. Then, a thin metal film and a thin copper film are formed in sequence on the insulating layer. The thin copper film is subsequently laminated with a dry film or the like, and exposed and developed to form a plating resist thereon that have patterns opposite to conductor patterns which are formed in a subsequent step. This is followed by forming conductor patterns made of copper, by electrolytic plating using an electrolytic copper sulfate plating solution, on the surfaces of the thin copper film where the plating resist is not formed. The plating resist is then removed by, for example, stripping. After this, the thin copper film is held at a temperature of not less than 200° C. and not more than 300° C. for approximately an hour to be thermally treated. Then, the thin copper film and the thin metal film are removed by chemical etching except the portions under the conductor patterns.Type: ApplicationFiled: July 1, 2005Publication date: January 5, 2006Inventors: Kei Nakamura, Takeshi Yamato
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Publication number: 20050244620Abstract: A wired circuit board which is formed so that even when a wired circuit pattern is formed at a fine pitch and then a tin plating layer is formed on the wired circuit pattern by the electroless tin plating, a wiring of the wired circuit pattern can be prevented from being stripped, and a production method of the same wired circuit board. After a thin metal film 2 formed of nickel-chromium alloy having a chromium content of 8-20 weight % is formed on an insulating layer 1, a wired circuit pattern 4 of copper is formed on the thin metal film 2. Then, a tin plating layer 5 is formed on exposed surfaces of the wired circuit pattern 4 by electroless tin plating.Type: ApplicationFiled: April 19, 2005Publication date: November 3, 2005Applicant: Nitto Denko CorporationInventors: Makoto Tsunekawa, Kei Nakamura, Keiko Toyozawa, Takeshi Yamato, Toshikazu Baba
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Publication number: 20050067293Abstract: A producing method of a flexible wired circuit board that can prevent the formation of a gap between an elongate substrate and a stiffener sheet bonded thereto to prevent contamination of the flexible wired circuit board obtained. In the process subsequent to the process of forming a conductive pattern 3 on a surface of the elongate substrate 1 by the semi-additive process using electrolysis plating and then annealing the elongate substrate 1 with the conductive pattern 3 in its wound up state, a stiffener sheet 9 having a width narrower than the elongate substrate 1 is bonded to the back side of the elongate substrate 1. Thereafter, an oxidized film formed on a surface of the conductive pattern 3 is removed and then a solder resist 11 is formed thereon. This prevents the strip of the stiffener sheet 9 from the elongate substrate 1 and in turn prevents etching solution or developing solution from entraining in a gap therebetween.Type: ApplicationFiled: September 28, 2004Publication date: March 31, 2005Inventors: Toshiki Naito, Yoshifumi Shinogi, Takeshi Yamato
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Publication number: 20040221448Abstract: A method for producing a wired circuit board that can provide improved productivity and economical efficiency, while preventing the forming failure of the wired circuit board due to which when a conductor layer is formed by plating, the plating material is caused to penetrate under the plating resist or the plating resist is caused to strip. In the method, after a thin conductor film 2 is formed on an insulating base layer 1, liquid solution of photosensitive resist is applied to the thin conductor film 2 and then dried, thereby forming the first plating resist layer 3 on the thin conductor film 2. Then, a film of photosensitive resist is adhesively bonded to the first plating resist layer 3, thereby forming the second plating resist layer 4. Thereafter, the first and the second plating resist layers 3, 4 are formed into a reversal pattern to a wired circuit pattern by a photographic process.Type: ApplicationFiled: April 29, 2004Publication date: November 11, 2004Inventors: Toshiki Naito, Hiroshi Yamazaki, Takeshi Yamato
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Patent number: 6388201Abstract: To provide a wired circuit board capable of surely preventing occurrence of a short circuit between a metal terminal layer and a metal supporting layer with a simple construction, to provide improvement in connection reliability and in voltage proof property, a wired circuit board comprises a base layer formed on a supporting board, a conductive layer formed on the base layer, a surface of the conductive layer being exposed by opening the supporting board and the base layer, and a metal plated layer formed on the conductive layer exposed in the openings of the supporting board and the base layer, wherein a specified space is defined between a periphery of the metal plated layer and a periphery of the opening of the supporting board.Type: GrantFiled: May 30, 2001Date of Patent: May 14, 2002Assignee: Nitto Denko CorporationInventors: Takeshi Yamato, Kenichiro Ito
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Publication number: 20020007961Abstract: To provide a wired circuit board capable of surely preventing occurrence of a short circuit between a metal terminal layer and a metal supporting layer with a simple construction, to provide improvement in connection reliability and in voltage proof property, a wired circuit board comprises a base layer formed on a supporting board, a conductive layer formed on the base layer, a surface of the conductive layer being exposed by opening the supporting board and the base layer, and a metal plated layer formed on the conductive layer exposed in the openings of the supporting board and the base layer, wherein a specified space is defined between a periphery of the metal plated layer and a periphery of the opening of the supporting board.Type: ApplicationFiled: May 30, 2001Publication date: January 24, 2002Inventors: Takeshi Yamato, Kenichiro Ito