Abstract: An active matrix substrate in which step-caused disconnection of a metal film in a contact hole does not easily occur includes a first to third insulating films and first to third metal films on a glass substrate and a contact hole electrically connecting the first and second metal film, the contact hole including first to third hole present respectively in the first to third insulating films, the first and third metal films being in contact with each other inside the first hole, the second insulating film and an oxide semiconductor film overlapping with each other in a region below the third hole, the second and third metal films being in contact with each other in a region above the first insulating film and either inside or below the third hole.

Abstract: A display device includes a first voltage primary wiring line that supplies a first voltage to respective pixel circuits of a display unit and a second voltage primary wiring line that supplies a second voltage to respective pixel circuits. An end portion of an unrolled area of the display unit, positioned on an opposite side with respect to a rolling mechanism, is provided as an edge portion. At least one of the first voltage primary wiring line and the second voltage primary wiring line is electrically connected to pixel circuits arranged at the edge portion first, out of the plurality of pixel circuits.

Abstract: A flexible display device has, in a folding portion, a slit that partitions a second electrode provided in common for a plurality of pixels, between a plurality of display units. In a plan view, in the slit, at least one of an organic insulating film, banks, and an organic layer has a slit, and a bulging portion formed by the organic insulating film and the banks is provided so as to surround each of the partitioned second electrodes.

Abstract: Provided are an active-matrix substrate having a reliable line connection structure, a method for producing the same, and a display device including the same. A first metal line 122 and a second metal line 125 are electrically connected via an IGZO layer 124 rendered conductive. In this case, the second metal line 125 is isolated from an ITO layer 109 without contacting the ITO layer 109 because there are a passivation layer 107 and an organic insulating film 108 formed between the second metal line 125 and the ITO layer 109. Thus, no contact fault due to electric corrosion occurs between an aluminum layer 125a of the second metal line 125 and the ITO layer 109, whereby a reliable line connection structure is achieved.

Abstract: A display device includes a first voltage primary wiring line that supplies a first voltage to respective pixel circuits of a display unit and a second voltage primary wiring line that supplies a second voltage to respective pixel circuits. An end portion of an unrolled area of the display unit, positioned on an opposite side with respect to a rolling mechanism, is provided as an edge portion. At least one of the first voltage primary wiring line and the second voltage primary wiring line is electrically connected to pixel circuits arranged at the edge portion first, out of the plurality of pixel circuits.

Abstract: Openings, which are provided on the inner sides of anode electrodes formed in a display region, are larger than openings, which are provided on the inner sides of anode electrodes formed in a peripheral display region. A light-emitting layer formed in the display region has equal shape and equal size to a light-emitting layer formed in the peripheral display region.

Abstract: A semiconductor device provided in a pixel circuit of a display device includes, in order from a lower side: a substrate; an LTPS layer; a first gate insulating layer; a first metal layer; a first flattened layer; a second gate insulating layer; an oxide semiconductor layer; a second metal layer; a passivation layer; and a third metal layer. The gate electrode layer of an LTPS-TFT and the gate electrode of an oxide semiconductor TFT are formed by the first metal layer.

Abstract: A flexible display device has, in a folding portion, a slit that partitions a second electrode provided in common for a plurality of pixels, between a plurality of display units. In a plan view, in the slit, at least one of an organic insulating film, banks, and an organic layer has a slit, and a bulging portion formed by the organic insulating film and the banks is provided so as to surround each of the partitioned second electrodes.

Abstract: Provided are an active-matrix substrate having a reliable line connection structure, a method for producing the same, and a display device including the same. A first metal line 122 and a second metal line 125 are electrically connected via an IGZO layer 124 rendered conductive. In this case, the second metal line 125 is isolated from an ITO layer 109 without contacting the ITO layer 109 because there are a passivation layer 107 and an organic insulating film 108 formed between the second metal line 125 and the ITO layer 109. Thus, no contact fault due to electric corrosion occurs between an aluminum layer 125a of the second metal line 125 and the ITO layer 109, whereby a reliable line connection structure is achieved.

Abstract: A semiconductor device (100) according to the present invention includes a plurality of source lines (16), a thin film transistor (50A), and a diode element (10A) that electrically connects two source lines (16) among the plurality of source lines (16). A connection region (26) in which the source lines (16) and the diode element (10A) are connected to each other includes a first electrode (3), a second electrode (6a), a third electrode (9a), and a fourth electrode (9b). A part of each source line (16) is a source electrode of the thin film transistor (50A), and the second electrode (6a) and the source lines (16) are formed separately from each other.

Abstract: An object of this invention is to provide a semiconductor device in which TFTs with high mobility are arranged in both of display and peripheral circuit areas. A semiconductor device fabricating method according to the present invention includes the steps of: irradiating an amorphous silicon layer (34) with energy, thereby obtaining a microcrystalline silicon layer; and forming a doped semiconductor layer (35) on the amorphous silicon layer (34). In the step of irradiating, the amorphous silicon layer (34) is irradiated with energy that has a first quantity, thereby forming a first microcrystalline silicon layer (34A) including a channel layer for a first TFT (30A), and is also irradiated with energy that has a second quantity, which is larger than the first quantity, thereby forming a second microcrystalline silicon layer (34B) including a channel layer for a second TFT (30B).

Abstract: A semiconductor device (18) includes: a gate electrode (102) formed on a substrate (101); a semiconductor layer (104) formed above the gate electrode (102) and including a source region, a drain region, and a channel region; a source electrode (106) connected to the source region above the semiconductor layer (104); and a drain electrode (107) connected to the drain region above the semiconductor layer (104). The semiconductor layer (104) has, at a portion overlapping the drain electrode (107), a protrusion that protrudes outward along an extending direction of a drain line drawn out from the drain electrode (107). At an outside of the channel region sandwiched between the drain electrode (107) and the source electrode (106), the semiconductor layer (104) has an adjustment portion where an outer boundary of the semiconductor layer (104) is positioned more inward than an outer boundary of the gate electrode (102).

Abstract: The present invention has an object of providing a TFT in which generation of an OFF current is reduced by an efficient manufacturing method. A thin film transistor 100 according to the present invention has a gate electrode 12 formed on a substrate 10, an insulating layer 14 formed on the gate electrode 12, a microcrystalline amorphous silicon layer 18 and an amorphous silicon layer 16 that are formed on the insulating layer 14, a semiconductor layer 20 containing an impurity formed on the amorphous silicon layer 16, and a source electrode 22A and a drain electrode 22B that are formed on the semiconductor layer 20 containing an impurity. The microcrystalline amorphous silicon layer 18 and the semiconductor layer 20 containing an impurity are connected to each other through the amorphous silicon layer 16 without being in direct contact with each other.

Abstract: A semiconductor device (100) according to the present invention includes a plurality of source lines (16), a thin film transistor (50A), and a diode element (10A) that electrically connects two source lines (16) among the plurality of source lines (16). A connection region (26) in which the source lines (16) and the diode element (10A) are connected to each other includes a first electrode (3), a second electrode (6a), a third electrode (9a), and a fourth electrode (9b). A part of each source line (16) is a source electrode of the thin film transistor (50A), and the second electrode (6a) and the source lines (16) are formed separately from each other.

Abstract: Disclosed is a high-quality, efficiently manufacturable thin film transistor in which leakage current is minimized. The thin film transistor is provided with a semiconductor layer (34) that contains a channel region (34C) having a microcrystalline semiconductor; source and drain contact layers (35S and 35D) that contains impurities; a first source metal layer (36S) and a first drain metal layer (36D), and a second source metal layer (37S) and a second drain metal layer (37D). The end portion of the second metal source layer (37S) is located at a position receded from the end portion of the first metal source layer (36S) and the end portion of the second drain metal layer (37D) is located at a position receded from the end portion of the first drain metal layer (36D). The semiconductor layer (34) contains low concentration impurity diffusion regions formed near the end portions of the aforementioned source contact layer (35S) and drain contact layer (35D).

Abstract: The present invention has an object of providing a TFT in which generation of an OFF current is reduced by an efficient manufacturing method. A thin film transistor 100 according to the present invention has a gate electrode 12 formed on a substrate 10, an insulating layer 14 formed on the gate electrode 12, a microcrystalline amorphous silicon layer 18 and an amorphous silicon layer 16 that are formed on the insulating layer 14, a semiconductor layer 20 containing an impurity formed on the amorphous silicon layer 16, and a source electrode 22A and a drain electrode 22B that are formed on the semiconductor layer 20 containing an impurity. The microcrystalline amorphous silicon layer 18 and the semiconductor layer 20 containing an impurity are connected to each other through the amorphous silicon layer 16 without being in direct contact with each other.

Abstract: The disclosed method for manufacturing an active matrix substrate includes a step in which a first mask is used to pattern a first conductive layer G, CS, and S, a step in which a second mask is used to pattern a first insulating layer, a step in which a third mask is used to pattern a semiconductor layer, a step in which a fourth mask is used to pattern a second conductive later, a step in which a fifth mask is used to pattern a second insulating layer, and a step in which a sixth mask is used to pattern a third conductive layer.

Abstract: A semiconductor device (18) includes: a gate electrode (102) formed on a substrate (101); a semiconductor layer (104) formed above the gate electrode (102) and including a source region, a drain region, and a channel region; a source electrode (106) connected to the source region above the semiconductor layer (104); and a drain electrode (107) connected to the drain region above the semiconductor layer (104). The semiconductor layer (104) has, at a portion overlapping the drain electrode (107), a protrusion that protrudes outward along an extending direction of a drain line drawn out from the drain electrode (107). At an outside of the channel region sandwiched between the drain electrode (107) and the source electrode (106), the semiconductor layer (104) has an adjustment portion where an outer boundary of the semiconductor layer (104) is positioned more inward than an outer boundary of the gate electrode (102).

Abstract: The present invention provides an active matrix substrate that is capable of reliably connecting a plurality of conductive layers that are arranged with an insulating layer therebetween. The active matrix substrate of the present invention has a first conductive layer (CS) and a second conductive layer (30), and an insulating layer (22) formed to cover the first conductive layer (CS) is provided. The first conductive layer (CS) has an end portion (CS1) formed to protrude within an opening portion (H1) formed in the insulating layer (22), and the second conductive layer (30) is provided to cover at least a part of the edge of the opening portion (H1) and to be connected directly to the end portion (CS1) of the first conductive layer (CS) within the opening portion (H1).

Abstract: An object of this invention is to provide a semiconductor device in which TFTs with high mobility are arranged in both of display and peripheral circuit areas. A semiconductor device fabricating method according to the present invention includes the steps of: irradiating an amorphous silicon layer (34) with energy, thereby obtaining a microcrystalline silicon layer; and forming a doped semiconductor layer (35) on the amorphous silicon layer (34). In the step of irradiating, the amorphous silicon layer (34) is irradiated with energy that has a first quantity, thereby forming a first microcrystalline silicon layer (34A) including a channel layer for a first TFT (30A), and is also irradiated with energy that has a second quantity, which is larger than the first quantity, thereby forming a second microcrystalline silicon layer (34B) including a channel layer for a second TFT (30B).