Abstract: To set a best oscillation state of a voltage-controlled oscillator (VCO) circuit, it is necessary to evaluate variability of manufactured ICs to specify set values based on the variability. Provided is an oscillator including: a terminal receiving a first signal; a VCO coupled to the terminal, the VCO oscillating to generate a second signal and to change a frequency of the second signal in response to an amplitude of the first signal, and revealing gain-slope characteristics in the frequency of the second signal versus the amplitude of the first signal; and a control circuit coupled to the VCO to alter the gain-slope characteristics in response to the amplitude of the first signal, the VCO having so-called self regulating characteristics in which the VCO is locked up based on the variability of the manufactured ICs without depending on external control.

Abstract: Disclosed is a PLL circuit of a small circuit size capable of generating clock including a jitter component with ease. A phase comparator 11 compares the phase of an input reference clock signal CKR to the phase of a signal fed back from a frequency divider 14 to route an output signal corresponding to the phase difference to a filter unit 12. The filter unit 12 detects a low frequency component of the output signal of the phase comparator 11 to route the so detected component to a voltage controlled oscillator 13. The voltage controlled oscillator 13 generates, as an output signal CKF, an oscillation signal of an oscillation frequency which is controlled on the basis of the output voltage of the filter unit 12. The frequency divider 14 divides the frequency of the output signal CKF to output the resulting signal to the phase comparator 11.

Abstract: To set a best oscillation state of a voltage-controlled oscillator (VCO) circuit, it is necessary to evaluate variability of manufactured ICs to specify set values based on the variability. Provided is an oscillator including: a terminal receiving a first signal; a VCO coupled to the terminal, the VCO oscillating to generate a second signal and to change a frequency of the second signal in response to an amplitude of the first signal, and revealing gain-slope characteristics in the frequency of the second signal versus the amplitude of the first signal; and a control circuit coupled to the VCO to alter the gain-slope characteristics in response to the amplitude of the first signal, the VCO having so-called self regulating characteristics in which the VCO is locked up based on the variability of the manufactured ICs without depending on external control.

Abstract: Disclosed is a PLL circuit of a small circuit size capable of generating clock including a jitter component with ease. A phase comparator 11 compares the phase of an input reference clock signal CKR to the phase of a signal fed back from a frequency divider 14 to route an output signal corresponding to the phase difference to a filter unit 12. The filter unit 12 detects a low frequency component of the output signal of the phase comparator 11 to route the so detected component to a voltage controlled oscillator 13. The voltage controlled oscillator 13 generates, as an output signal CKF, an oscillation signal of an oscillation frequency which is controlled on the basis of the output voltage of the filter unit 12. The frequency divider 14 divides the frequency of the output signal CKF to output the resulting signal to the phase comparator 11.