Patents by Inventor Taketo Heishi
Taketo Heishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8612958Abstract: A compiler, which corresponds to a recent processor having a multithread function, that enables execution of efficient instruction scheduling and allows a programmer to control the instruction scheduling includes: an instruction scheduling directive receiving unit which receives, from a programmer, a directive for specifying an instruction scheduling method; and an instruction scheduling unit which executes, conforming to one of instruction scheduling methods, instruction scheduling of rearranging intermediate codes corresponding to the source program. The instruction scheduling unit selects one of instruction scheduling methods according to the directive received by the instruction scheduling directive receiving unit, and executes instruction scheduling conforming to the selected instruction scheduling method.Type: GrantFiled: June 17, 2011Date of Patent: December 17, 2013Assignee: Panasonic CorporationInventors: Taketo Heishi, Shohei Michimoto, Teruo Kawabata
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Patent number: 8587336Abstract: A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.Type: GrantFiled: November 14, 2006Date of Patent: November 19, 2013Assignee: Semiconductor Technology Academic Research CenterInventors: Toshinori Sueyoshi, Masahiro Iida, Motoki Amagasaki, Kazuhiko Taketa, Taketo Heishi, Nobuharu Suzuki
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Patent number: 8418157Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.Type: GrantFiled: February 16, 2010Date of Patent: April 9, 2013Assignee: Panasonic CorporationInventors: Hajime Ogawa, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi
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Patent number: 8402445Abstract: The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions.Type: GrantFiled: December 7, 2010Date of Patent: March 19, 2013Assignee: Panasonic CorporationInventors: Yoko Makiyori, Taketo Heishi, Akira Takuma
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Patent number: 8392905Abstract: The present invention effectively utilizes auxiliary registers and provides a compiler system which secures error detectability when the auxiliary registers are shared for plural uses. The instruction definition resource configuring unit configures, as preparation for processing by the register assigning unit, respective resources such as a register to be defined or referred to by for each instruction in an intermediate code. The instruction definition resource configuring unit detects possibility of instructions each of which is to be decomposed into plural instructions. As for an instruction to be possibly decomposed, the instruction definition resource configuring unit configures a corresponding register in the intermediate code, assuming the corresponding register used for the decomposition to be defined and referred. The register assigning unit uses the register as a general register as far as a live range of the register used for the decomposition does not overlap.Type: GrantFiled: March 14, 2008Date of Patent: March 5, 2013Assignee: Panasonic CorporationInventors: Taketo Heishi, Shohei Michimoto, Yukio Iimura, Yasuhiro Yamamoto
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Patent number: 8286145Abstract: A program re-writing method which re-writes an inputted program into a program for a processor for controlling whether or not a process is executed based on a yes or no execution flag, said program re-writing method including: inserting a comparison process into the inputted program, the comparison process comparing first address information, which is memory address information accessed by a first memory access process included in the inputted program, and second address information, which is address information of a memory accessed by a second memory access process included in the inputted program, and writing a comparison result into the yes or no execution flag; and inserting a yes or no execution flag-attached logic preservation process into the inputted program, the yes or no execution flag-attached logic preservation process being a process executed based on a value of the yes or no execution flag and preserving the same result as a result of the inputted program when executed.Type: GrantFiled: April 22, 2008Date of Patent: October 9, 2012Assignee: Panasonic CorporationInventors: Teruo Kawabata, Masatsugu Daimon, Taketo Heishi, Hajime Ogawa
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Patent number: 8151254Abstract: An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.Type: GrantFiled: April 24, 2007Date of Patent: April 3, 2012Assignee: Panasonic CorporationInventors: Taketo Heishi, Toshiyuki Sakata, Hajime Ogawa, Ryoko Miyachi, Shuji Miyasaka, Tomokazu Ishikawa
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Publication number: 20110276787Abstract: A multithread processor for executing, in parallel, instructions included in a plurality of threads includes: a calculating group including a plurality of calculators each of which is for executing an instruction; instruction grouping units which classify, for each thread, the instructions included in the thread into groups each of which includes instructions that are simultaneously executable by the calculators; a thread selecting unit which selects, per execution cycle of the multithread processor, a thread including instructions to be issued to the calculators, from among the threads, by controlling execution frequency for executing the instructions included in the threads; and an instruction issuing unit which issues, to the calculators, per execution cycle of the multithread processor, the instructions classified into each of the groups and being among the instructions included in the thread selected by the thread selecting unit.Type: ApplicationFiled: July 20, 2011Publication date: November 10, 2011Applicant: PANASONIC CORPORATIONInventors: Yoshihiro KOGA, Taketo HEISHI
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Publication number: 20110252410Abstract: A compiler, which corresponds to a recent processor having a multithread function, that enables execution of efficient instruction scheduling and allows a programmer to control the instruction scheduling includes: an instruction scheduling directive receiving unit which receives, from a programmer, a directive for specifying an instruction scheduling method; and an instruction scheduling unit which executes, conforming to one of instruction scheduling methods, instruction scheduling of rearranging intermediate codes corresponding to the source program. The instruction scheduling unit selects one of instruction scheduling methods according to the directive received by the instruction scheduling directive receiving unit, and executes instruction scheduling conforming to the selected instruction scheduling method.Type: ApplicationFiled: June 17, 2011Publication date: October 13, 2011Applicant: PANASONIC CORPORATIONInventors: Taketo HEISHI, Shohei MICHIMOTO, Teruo KAWABATA
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Publication number: 20110078664Abstract: The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicant: PANASONIC CORPORATIONInventors: Yoko MAKIYORI, Taketo HEISHI, Akira TAKUMA
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Patent number: 7877743Abstract: The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions.Type: GrantFiled: November 13, 2006Date of Patent: January 25, 2011Assignee: Panasonic CorporationInventors: Yoko Makiyori, Taketo Heishi, Akira Takuma
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Patent number: 7856629Abstract: A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.Type: GrantFiled: May 24, 2006Date of Patent: December 21, 2010Assignee: Panasonic CorporationInventors: Shohei Michimoto, Taketo Heishi, Hajime Ogawa, Teruo Kawabata
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Patent number: 7823142Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.Type: GrantFiled: October 7, 2005Date of Patent: October 26, 2010Assignee: Panasonic CorporationInventors: Shuichi Takayama, Hajime Ogawa, Kenichi Kawaguchi, Nobuo Higaki, Kensuke Odani, Tetsuya Tanaka, Shinya Miyaji, Taketo Heishi
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Patent number: 7761692Abstract: In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.Type: GrantFiled: June 14, 2006Date of Patent: July 20, 2010Assignee: Panasonic CorporationInventors: Taketo Heishi, Shuichi Takayama, Tetsuya Tanaka, Hajime Ogawa, Nobuo Higaki
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Publication number: 20100175056Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.Type: ApplicationFiled: February 16, 2010Publication date: July 8, 2010Inventors: Hajime OGAWA, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi
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Patent number: 7698696Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.Type: GrantFiled: June 30, 2003Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Hajime Ogawa, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi
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Patent number: 7689976Abstract: A compiler capable of increasing the hit rate of the cache memory is provided that targets a computer having a cache memory, and that converts a source program into an object program. The compiler causes a computer to analyze group information that is used for grouping data objects included in the source program, and places the data objects into groups based on a result of the analysis. The compiler also causes the computer to generate an object program based on a result of the grouping, where the object program does not allow data objects belonging to different groups to be laid out in any blocks with the same set number on the cache memory.Type: GrantFiled: September 28, 2004Date of Patent: March 30, 2010Assignee: Panasonic CorporationInventors: Yasuhiro Yamamoto, Hajime Ogawa, Taketo Heishi, Shohei Michimoto
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Patent number: 7594099Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: GrantFiled: August 31, 2007Date of Patent: September 22, 2009Assignee: Panasonic CorporationInventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Patent number: RE41751Abstract: A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1tA unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k?1)th unit field in the same parallel execution code.Type: GrantFiled: November 24, 2003Date of Patent: September 21, 2010Assignee: Panasonic CorporationInventors: Taketo Heishi, Tetsuya Tanaka, Nobuo Higaki, Shuichi Takayama, Kensuke Odani
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Patent number: RE45199Abstract: A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.Type: GrantFiled: September 14, 2012Date of Patent: October 14, 2014Assignee: Panasonic CorporationInventors: Shohei Michimoto, Taketo Heishi, Hajime Ogawa, Teruo Kawabata