Abstract: A semiconductor intergrated circuit device is comprised a main portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns and a sub memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns, wherein at least one of address input terminals assigning rows or columns of the main memory portion and at least one of address input terminals assigning rows or columns of the sub memory portion are commonly used and a total number of address input terminals is equal to or smaller than the number of address input terminals assigning rows or columns of the main memory portion. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor memory device includes a plurality of memory cell groups, each of the memory cell groups being selectable by an address signal or an internal control signal and a plurality of registers coupled to a corresponding one of the memory cell groups, each of the registers storing a data input/output mode to set the data input/output mode for the corresponding one of the memory cell groups.

Abstract: A semiconductor integrated circuit device includes a main memory portion, a sub memory portion including a plurality of memory cell groups and a bidirectional data transfer circuit provided between the main memory portion and the sub memory portion. A bi-directional data transfer between an arbitrary area of the main memory portion and the plurality of the memory cell groups, and a read or write operation are performed simultaneously. Therefore, the semiconductor integrated circuit device has a main memory suitable for being accessed from a plurality of memory masters or data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor memory device for improving the transmission data rate of a data input and output bus, and a memory module including the same, are provided. The memory module includes a plurality of clock synchronous memory devices that share a single data bus line. More specifically, the memory module includes a printed circuit board having an electrical connector including the data bus line, a first set of synchronous memory devices arrayed on the printed circuit board, a second set of synchronous memory devices arrayed on the print circuit board, and a clock signal generator electrically connected to the first and second set of synchronous memory devices. The clock signal generator operates to receive a clock signal from the electrical connector and to generate a first clock signal that is matched with the received clock signal and a second clock signal that is delayed with respect to the received clock signal for half the period of the received clock signal.

Abstract: A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: The present invention provides a double data rate synchronous dynamic random-access memory (SDRAM) which allows a data mask signal to mask a data signal on a bit basis during write operation at a low frequency while maintaining compatibility with conventional SDRAMs and which increases the margin of the DRAM and the overall system. The double data rate synchronous dynamic random-access memory has address signal lines over which an unused column address signal is sent to a byte mask data latch circuit for use as the mask signal.

Abstract: A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion constructed with memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion constructed with a plurality of memory cells arranged in a plurality of rows and in a plurality of columns and a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, wherein the data transfer bus lines in a memory cell area of the main memory portion are arranged in parallel to bit lines in a column direction and connected to the bit lines through a column selection circuit. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion, a sub memory portion composed of a plurality of memory cell groups and a bi-directional data transfer circuit provided between the main memory portion and the sub memory portion, wherein power source voltages of the main memory portion and the sub memory portion are different from each other. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.