Abstract: A light source device includes a mounted substrate which is a multi-layered substrate, a semiconductor light-emitting device which emits a laser beam, a wavelength-converting member which radiates fluorescence by being irradiated with the laser beam emitted from the semiconductor light-emitting device as an excitation light, a state detection circuit, an electric field effect type transistor which adjusts an electric current amount applied to the semiconductor light-emitting device upon receipt of an output from the state detection circuit, and an external connecting member, and the semiconductor light-emitting device, the state detection circuit, the transistor, and the external connecting member are mounted on the single mounted substrate.

Abstract: A light source device includes a mounted substrate which is a multi-layered substrate, a semiconductor light-emitting device which emits a laser beam, a wavelength-converting member which radiates fluorescence by being irradiated with the laser beam emitted from the semiconductor light-emitting device as an excitation light, a state detection circuit, an electric field effect type transistor which adjusts an electric current amount applied to the semiconductor light-emitting device upon receipt of an output from the state detection circuit, and an external connecting member, and the semiconductor light-emitting device, the state detection circuit, the transistor, and the external connecting member are mounted on the single mounted substrate.

Abstract: A semiconductor integrated circuit that suppresses steep changes of an output voltage when starting of a charge pump circuit to suppress transient displacement of output of a circuit block operating independently of the charge pump circuit is provided. A semiconductor integrated circuit has: a charge pump circuit which charges a first capacitor with an input voltage, transfers a charge accumulated in the first capacitor to a second capacitor, outputs, as an output voltage, a voltage of the second capacitor, and is capable of changing over a capability of charging the second capacitor; a first circuit block that receives a positive voltage and a grounding potential; and a second circuit block that receives the positive voltage and the output voltage of the charge pump. The semiconductor integrated circuit suppresses the charging capability by the charge pump circuit when starting of the charge pump circuit.

Abstract: A semiconductor integrated circuit includes a charge pump circuit that repeats charge and discharge of a capacitor based on a clock signal when an ON/OFF control voltage is ON; a first delay circuit that delays the ON/OFF control voltage; a switch that shorts an output of the charge pump circuit and a GND input terminal when the delayed ON/OFF control voltage is OFF and opens when the delayed ON/OFF control voltage is ON; a first circuit block that is driven by a power voltage which is supplied from a power source input terminal and the charge pump circuit; and a second circuit block that is driven by a power voltage which is supplied from the power source input terminal and the GND input terminal. The first and second circuit blocks are mounted on the same semiconductor integrated circuit chip.

Abstract: A semiconductor integrated circuit that suppresses steep changes of an output voltage when starting of a charge pump circuit to suppress transient displacement of output of a circuit block operating independently of the charge pump circuit is provided. A semiconductor integrated circuit has: a charge pump circuit which charges a first capacitor with an input voltage, transfers a charge accumulated in the first capacitor to a second capacitor, outputs, as an output voltage, a voltage of the second capacitor, and is capable of changing over a capability of charging the second capacitor; a first circuit block that receives a positive voltage and a grounding potential; and a second circuit block that receives the positive voltage and the output voltage of the charge pump. The semiconductor integrated circuit suppresses the charging capability by the charge pump circuit when starting of the charge pump circuit.

Abstract: A step-down voltage output circuit preventing: latch-up phenomenon in a load circuit for a period between a power-supply activation and complete start of a charge pump circuit; and rapid change of a substrate potential when a step-down voltage output is changed from ON to OFF. The step-down voltage output circuit has a timer circuit that operates depending on control signals and a timer period; a first N-channel MOS transistor in which a source is connected to a step-down voltage output terminal, a drain is connected to ground, a gate is connected to a power-supply voltage input terminal through a resistance; and a second N-channel MOS transistor in which a source is connected to the step-down voltage output terminal, a drain is connected to the gate of the first N-channel MOS transistor, and a gate is connected to an output terminal of the timer circuit.

Abstract: To provide a step-down voltage output circuit which causes no latch-up phenomenon for the period between activation of a power supply and complete start of operation of a charge pump circuit. The step-down voltage output circuit of the present invention has the charge pump circuit with a first oscillator; a timer circuit in which a timer period is set according to an oscillating frequency of the above-mentioned first oscillator; and an N-channel MOS transistor in which one N-type diffusion layer is connected to an output terminal of the above-mentioned charge pump circuit, the other N-type diffusion layer is connected to ground potential, and a gate electrode is connected to an output terminal of the above-mentioned timer circuit to become conductive for the above-mentioned timer period.

Abstract: A step-down voltage output circuit preventing: latch-up phenomenon in a load circuit for a period between a power-supply activation and complete start of a charge pump circuit; and rapid change of a substrate potential when a step-down voltage output is changed from ON to OFF. The step-down voltage output circuit has a timer circuit that operates depending on control signals and a timer period; a first N-channel MOS transistor in which a source is connected to a step-down voltage output terminal, a drain is connected to ground, a gate is connected to a power-supply voltage input terminal through a resistance; and a second N-channel MOS transistor in which a source is connected to the step-down voltage output terminal, a drain is connected to the gate of the first N-channel MOS transistor, and a gate is connected to an output terminal of the timer circuit.

Abstract: A semiconductor integrated circuit includes a charge pump circuit that repeats charge and discharge of a capacitor based on a clock signal when an ON/OFF control voltage is ON; a first delay circuit that delays the ON/OFF control voltage; a switch that shorts an output of the charge pump circuit and a GND input terminal when the delayed ON/OFF control voltage is OFF and opens when the delayed ON/OFF control voltage is ON; a first circuit block that is driven by a power voltage which is supplied from a power source input terminal and the charge pump circuit; and a second circuit block that is driven by a power voltage which is supplied from the power source input terminal and the GND input terminal. The first and second circuit blocks are mounted on the same semiconductor integrated circuit chip.

Abstract: An AGC circuit, which does not require any signal integration circuit comprised of a capacitor and a resistor, is provided. To achieve the above object, when amplifying or attenuating input signal by a variable gain control circuit controlled by the gain control voltage, output signal of the variable gain amplifier circuit is rectified by a rectification circuit, the output signal of the rectification circuit is compared to an arbitrary set voltage by a voltage comparator. The up-count operation and the down-count operation of the up/down counter is controlled to changeover by the output signal of the voltage comparator, and a voltage corresponding to the count value of the up/down counter is output from the D/A conversion circuit. Thus, gain control voltage corresponding to the voltage output from the D/A conversion circuit is supplied to the variable gain amplifier circuit.

Abstract: In order that an amplifier with a gain proportional to source voltage is obtained, the drain-source voltages of first and second P-channel MOS-FETs are zero-biased, and a voltage shifted higher by the amount of the threshold voltage of the P-channel MOS-FET on the basis of a voltage obtained by dividing the power source voltage by resistors is applied to the positive input terminal of an operational amplifier. The gate of one of the first and second MOS-FETs is connected to a circuit ground, and a negative fixed voltage with reference to the potential obtained by dividing the power source voltage by resistors is applied to the gate of the other MOS-FET. The ON resistances of the two MOS-FETs are used as the input resistor and the feedback resistor of the operational amplifier, respectively.

Abstract: A rectified analog input signal is compared with a threshold voltage by a voltage comparator, and counting direction of an up/down counter is switched based on the comparison result, and a latch circuit retains an output of the up/down counter, and then an analog-digital converting circuit converts an output of the latch signal into a direct-current voltage. In addition, two input terminals, to which a clock for up-count operation and a clock for down-count operation are independently provided, is provided in the up/down counter, and a timing pulse generating circuit for determining reset timing of the up/down counting circuit and latch timing of the latch circuit is provided.

Abstract: To provide a step-down voltage output circuit which causes no latch-up phenomenon for the period between activation of a power supply and complete start of operation of a charge pump circuit. The step-down voltage output circuit of the present invention has the charge pump circuit with a first oscillator; a timer circuit in which a timer period is set according to an oscillating frequency of the above-mentioned first oscillator; and an N-channel MOS transistor in which one N-type diffusion layer is connected to an output terminal of the above-mentioned charge pump circuit, the other N-type diffusion layer is connected to ground potential, and a gate electrode is connected to an output terminal of the above-mentioned timer circuit to become conductive for the above-mentioned timer period.

Abstract: A rectified analog input signal is compared with a threshold voltage by a voltage comparator, and counting direction of an up/down counter is switched based on the comparison result, and a latch circuit retains an output of the up/down counter, and then an analog-digital converting circuit converts an output of the latch signal into a direct-current voltage. In addition, two input terminals, to which a clock for up-count operation and a clock for down-count operation are independently provided, is provided in the up/down counter, and a timing pulse generating circuit for determining reset timing of the up/down counting circuit and latch timing of the latch circuit is provided.

Abstract: An AGC circuit, which does not require any signal integration circuit comprised of a capacitor and a resistor, is provided. To achieve the above object, when amplifying or attenuating input signal by a variable gain control circuit controlled by the gain control voltage, output signal of the variable gain amplifier circuit is rectified by a rectification circuit, the output signal of the rectification circuit is compared to an arbitrary set voltage by a voltage comparator. The up-count operation and the down-count operation of the up/down counter is controlled to changeover by the output signal of the voltage comparator, and a voltage corresponding to the count value of the up/down counter is output from the D/A conversion circuit. Thus, gain control voltage corresponding to the voltage output from the D/A conversion circuit is supplied to the variable gain amplifier circuit.

Abstract: In order that an amplifier with a gain proportional to source voltage is obtained, the drain-source voltages of first and second P-channel MOS-FETs are zero-biased, and a voltage shifted higher by the amount of the threshold voltage of the P-channel MOS-FET on the basis of a voltage obtained by dividing the power source voltage by resistors is applied to the positive input terminal of an operational amplifier. The gate of one of the first and second MOS-FETs is connected to a circuit ground, and a negative fixed voltage with reference to the potential obtained by dividing the power source voltage by resistors is applied to the gate of the other MOS-FET. The ON resistances of the two MOS-FETs are used as the input resistor and the feedback resistor of the operational amplifier, respectively.