Abstract: According to one embodiment, the memory system includes a nonvolatile memory including a plurality of blocks, and a controller circuit that controls execution of a data writing process and a garbage collection process. Each of the blocks is an unit of erasure. The data writing process includes a process of writing user data into the nonvolatile memory in accordance with a request from an external member. The garbage collection process includes a process of moving valid data in at least a first block into a second block among the blocks and invalidating the valid data in the first block to be erasable. Upon receiving a data write request from the external member, the controller circuit controls a length of a waiting time to be provided before or after the data writing process within a period from receiving the write request to returning a response to the external member.

Abstract: According to one embodiment, when a command for committing data requested to be written is received from a host, a controller calculates a first value in a case where data has not been written up to a final page of a second block that is a multi-value recording block. The first value represents an amount or a data ratio of data written into the second block. The controller writes write data, which is written into a first block that is a binary-value recording block, up to a final page of the second block in a case where the first value is a first threshold or more.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface, an encoder configured to generate eight code words, and a writing control unit. The writing control unit causes the memory interface to perform a first writing and a second writing, and repeat the first writing and the second writing. The first writing writes a first symbol included in a first code word to a second page in a first word line. The second writing writes a second symbol included in a first code word to a first page in a third word line adjacent to a second word line adjacent to a first word line. Thus, the code words to be written are changed. The repeat of the first writing and the second writing is performed by shifting a word line at a write destination one by one.

Abstract: According to one embodiment, when a command for committing data requested to be written is received from a host, a controller calculates a first value in a case where data has not been written up to a final page of a second block that is a multi-value recording block. The first value represents an amount or a data ratio of data written into the second block. The controller writes write data, which is written into a first block that is a binary-value recording block, up to a final page of the second block in a case where the first value is a first threshold or more.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface, an encoder configured to generate eight code words, and a writing control unit. The writing control unit causes the memory interface to perform a first writing and a second writing, and repeat the first writing and the second writing. The first writing writes a first symbol included in a first code word to a second page in a first word line. The second writing writes a second symbol included in a first code word to a first page in a third word line adjacent to a second word line adjacent to a first word line. Thus, the code words to be written are changed. The repeat of the first writing and the second writing is performed by shifting a word line at a write destination one by one.

Abstract: A method and a device for controlling a non-volatile semiconductor memory device having a plurality of physical memory blocks are described. The control method includes forming a logical block including normal physical blocks and a defective physical block. Then read-only data (which can include system data and user data which is infrequently used) is targeted for a write to the defective physical block. Instead of actually writing the read-only data in the defective physical block, an error correction coding generated using the read-only data is stored in the normal physical blocks together with other data. When the read-only data is requested to be read, the read-only data is reproduced using the error correction coding.

Abstract: A logic circuit apparatus that allocates process capability to unit circuits operated in a time divisional manner, including a circuit arrangement information memory which stores circuit arrangement information corresponding to each of plurality of unit circuits, and a programmable logic circuit with a circuit arrangement which can be reconfigured by employing the circuit arrangement information while the programmable logic circuit is being operated, a process data memory which stores both input data and output data related to a process operation of each of the circuits, and a controller which monitors a storage amount of the input data and/or a storage amount of the output data corresponding to each unit circuit, and which controls reconfiguration of the circuit arrangement of the programmable logic circuit when the storage amount satisfies a certain condition.

Abstract: A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic circuits are each configured to have a changeable circuit component based on circuit data. Each programmable logic circuit has a different processing performance. The circuit data memory is used to store a plurality of circuit data and performance requirements for the circuit data. The control unit is configured to selectively assign the plurality of circuit data to the plurality of programmable logic circuits so that a total power of all programmable logic circuits minimizes on condition that the performance requirement of the circuit data assigned to each programmable logic circuit is within the processing performance of each programmable logic circuit.

Abstract: A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.

Abstract: A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.

Abstract: A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.

Abstract: A logic circuit apparatus that allocates process capability to unit circuits operated in a time divisional manner, including a circuit arrangement information memory which stores circuit arrangement information corresponding to each of plurality of unit circuits, and a programmable logic circuit with a circuit arrangement which can be reconfigured by employing the circuit arrangement information while the programmable logic circuit is being operated, a process data memory which stores both input data and output data related to a process operation of each of the circuits, and a controller which monitors a storage amount of the input data and/or a storage amount of the output data corresponding to each unit circuit, and which controls reconfiguration of the circuit arrangement of the programmable logic circuit when the storage amount satisfies a certain condition.

Abstract: A processor which performs data processings including a plurality of execution units, comprising a storage which stores data used for processings of the execution units and processing results by the execution units, by each of the execution units, a data processing part configured to acquire data of the execution units from said storage to perform the processings, and configured to output the processing results in said storage, an execution unit judgement part configured to determine whether or not said storage holds data used for the processings of a certain execution unit, and whether or not said storage has a vacant region capable of storing the processing result of the certain execution unit, and an execution unit determination part which determines an execution unit to be processed next among said plurality of execution units, based on a result judged by said execution unit judgement part.