Patents by Inventor Takuichiro SHITOMI

Takuichiro SHITOMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352232
    Abstract: Provided is a coil device having a first coil and a second coil insulated by an insulating film, and deformation of the insulating film is suppressed. A coil device includes: a first insulating film provided in contact with a first direction side of a substrate; a spiral-shaped first coil part provided in contact with a first direction side of the first insulating film; a second insulating film provided to cover a first direction side of the first coil part and the first direction side of the first insulating film where the first coil part is not provided; a spiral-shaped second coil part provided in contact with a first direction side of the second insulating film; and a groove provided on a surface on the first direction side of the second insulating film in a region inside an outer peripheral edge of the second coil part in plan view.
    Type: Application
    Filed: January 18, 2023
    Publication date: November 2, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yohei TORII, Manabu YOSHINO, Yasuo YAMAGUCHI, Takuichiro SHITOMI, Toshihiro IMASAKA
  • Publication number: 20230275133
    Abstract: A resistive field plate is arranged in a spiral shape in plan view so as to gradually approach an inner main electrode from an outer main electrode. The plurality of floating layers are arranged radially toward the low potential region around the high potential region in plan view. The resistive field plate is provided on the plurality of floating layers via an interlayer insulating film, and thus has a floating step reflecting a film thickness of each of the plurality of floating layers. That is, the resistive field plate is provided in such a manner that the floating step is repeatedly generated along the lapping direction.
    Type: Application
    Filed: December 15, 2022
    Publication date: August 31, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takuichiro SHITOMI, Manabu YOSHINO, Toshihiro IMASAKA
  • Patent number: 10418281
    Abstract: An object is to provide a technique for preventing an oxide film from being partly thin. A third oxide film is formed onto a nitride film in a first area; in addition, a fourth oxide film is formed onto a main surface in a second area. The third oxide film, the nitride film, and a first oxide film are removed from the first area using a mask. After the third oxide film, the nitride film, and the first oxide film are removed, a fifth oxide film is formed onto the main surface in the first area. The fifth oxide film is removed from the first area using a mask. After the fifth oxide film is removed, a sixth oxide film is formed onto the main surface in the first area.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 17, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takuichiro Shitomi
  • Publication number: 20190131174
    Abstract: An object is to provide a technique for preventing an oxide film from being partly thin. A third oxide film is formed onto a nitride film in a first area; in addition, a fourth oxide film is formed onto a main surface in a second area. The third oxide film, the nitride film, and a first oxide film are removed from the first area using a mask. After the third oxide film, the nitride film, and the first oxide film are removed, a fifth oxide film is formed onto the main surface in the first area. The fifth oxide film is removed from the first area using a mask. After the fifth oxide film is removed, a sixth oxide film is formed onto the main surface in the first area.
    Type: Application
    Filed: June 30, 2016
    Publication date: May 2, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventor: Takuichiro SHITOMI
  • Patent number: 9865513
    Abstract: A semiconductor device manufacturing method includes an element forming step of forming an element structure on a front surface of a substrate and forming a back structure on a back surface of the substrate, and a film forming step of performing film forming on a front surface of the element structure while measuring the temperature of the substrate by using a radiation thermometer that applies infrared rays of a wavelength ?i to the back structure to obtain an infrared emissivity of the substrate. The back structure has a first layer exposed to the outside and a second layer in contact with the first layer, the refractive index of the second layer being smaller than that of the first layer, and the layer thickness of the first layer is set in a range from (2n?1)?i/8 to (2n+1)?i/8, with n being a positive even number.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: January 9, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuichiro Shitomi, Kazuhisa Koga, Satoshi Rittaku
  • Publication number: 20170040229
    Abstract: A semiconductor device manufacturing method includes an element forming step of forming an clement structure on a front surface of a substrate and forming a back structure on a back surface of the substrate, and a film forming step of performing film forming on a front surface of the element structure while measuring the temperature of the substrate by using a radiation thermometer that applies infrared rays of a wavelength ?i to the back structure to obtain an infrared emissivity of the substrate. The back structure has a first layer exposed to the outside and a second layer in contact with the first layer, the refractive index of the second layer being smaller than that of the first layer, and the layer thickness of the first layer is set in a range from (2n?1)?i/8 to (2n+1)?i/8, with n being a positive even number.
    Type: Application
    Filed: May 21, 2014
    Publication date: February 9, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takuichiro SHITOMI, Kazuhisa KOGA, Satoshi RITTAKU
  • Patent number: 9082716
    Abstract: A method of manufacturing a semiconductor device, includes the steps of forming a top surface nitride film on a top surface of a substrate and a bottom surface nitride film on a bottom surface of the substrate, forming a protective film on the top surface nitride film, removing the bottom surface nitride film by wet etching while the top surface nitride film is being protected by the protective film, removing the protective film after the removing of the bottom surface nitride film, patterning the top surface nitride film so as to form an opening in the top surface nitride film, and forming a second oxide film on the bottom surface of the substrate while forming a first oxide film on a surface portion of the substrate which is exposed by the opening.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: July 14, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuichiro Shitomi, Yusuke Kawase, Junichi Yamashita, Manabu Yoshino
  • Patent number: 8952454
    Abstract: An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: February 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Shimizu, Junichi Yamashita, Takuichiro Shitomi
  • Publication number: 20150031208
    Abstract: A method of manufacturing a semiconductor device, includes the steps of forming a top surface nitride film on a top surface of a substrate and a bottom surface nitride film on a bottom surface of the substrate, forming a protective film on the top surface nitride film, removing the bottom surface nitride film by wet etching while the top surface nitride film is being protected by the protective film, removing the protective film after the removing of the bottom surface nitride film, patterning the top surface nitride film so as to form an opening in the top surface nitride film, and forming a second oxide film on the bottom surface of the substrate while forming a first oxide film on a surface portion of the substrate which is exposed by the opening.
    Type: Application
    Filed: April 4, 2014
    Publication date: January 29, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takuichiro SHITOMI, Yusuke KAWASE, Junichi YAMASHITA, Manabu YOSHINO
  • Publication number: 20130221439
    Abstract: An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.
    Type: Application
    Filed: November 9, 2012
    Publication date: August 29, 2013
    Inventors: Kazuhiro SHIMIZU, Junichi YAMASHITA, Takuichiro SHITOMI