Abstract: An AD converter converts an analogue input voltage into a digital value including a most significant bit to a least significant bit. The AD converter includes: a common node; a capacitive DAC; a comparator; a successive approximation controller; and an integrator. The integrator includes first to Xth integrating circuits connected in a cascade arrangement, where X is an integer greater than or equal to two, and at least one feedforward path that each samples a residual voltage and outputs the sampled residual voltage to one of the second to Xth integrating circuits.

Abstract: An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N?1) first sampling circuits out of the execution of the calibration.

Abstract: A time-interleaved analog-to-digital (AD) converter includes: N AD converters; a frequency divider that receives a clock signal and applies 1/N frequency division N to the received clock signal to generate N frequency-divided clock signals to be supplied to the N AD converters; at least (N?1) variable delay circuit that adjusts delay time for at least (N?1) frequency-divided clock signal; a low pass filter circuit or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N?1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.

Abstract: An AD converter converts an analogue input voltage into a digital value including a most significant bit to a least significant bit. The AD converter includes: a common node; a capacitive DAC; a comparator; a successive approximation controller; and an integrator. The integrator includes first to Xth integrating circuits connected in a cascade arrangement, where X is an integer greater than or equal to two, and at least one feedforward path that each samples a residual voltage and outputs the sampled residual voltage to one of the second to Xth integrating circuits.

Abstract: An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N?1) first sampling circuits out of the execution of the calibration.

Abstract: A time-interleaved analog-to-digital (AD) converter includes: N AD converters; a frequency divider that receives a clock signal and applies 1/N frequency division N to the received clock signal to generate N frequency-divided clock signals to be supplied to the N AD converters; at least (N?1) variable delay circuit that adjusts delay time for at least (N?1) frequency-divided clock signal; a low pass filter circuit or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N?1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.

Abstract: In a successive approximation AD converter, a noise generator outputs the output of a ?? modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.

Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.

Abstract: A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.

Abstract: A time integrator integrates time axis information represented by a phase difference between two signals. The time integrator includes a pulse generation circuit configured to convert a time difference between edges of two input signals to a difference between pulse widths of two pulse signals, and to output the two pulse signals, a load circuit having load characteristics changed by the two pulse signals, and an oscillation circuit coupled to the load circuit, and having an oscillation frequency changing in accordance with the load characteristics of the load circuit. An output of the oscillation circuit is output as a result of time integration.

Abstract: A time integrator integrates time axis information represented by a phase difference between two signals. The time integrator includes a pulse generation circuit configured to convert a time difference between edges of two input signals to a difference between pulse widths of two pulse signals, and to output the two pulse signals, a load circuit having load characteristics changed by the two pulse signals, and an oscillation circuit coupled to the load circuit, and having an oscillation frequency changing in accordance with the load characteristics of the load circuit. An output of the oscillation circuit is output as a result of time integration.

Abstract: An A/D converter having high accuracy and high throughput irrespective of characteristic variations of analog circuits is provided. The A/D converter includes a voltage-to-time converter configured to synchronize with a sampling clock signal and convert an input analog voltage to a time difference between two signals, and a plurality of time-to-digital converters each configured to convert the time difference between the two signals to a digital value. The plurality of time-to-digital converters operate in an interleaved manner.

Abstract: In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from ?(2n-1?1) to +(2n-1?1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.

Abstract: In a successive approximation AD converter, a noise generator outputs the output of a ?? modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.

Abstract: A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.

Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.

Abstract: In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from ?(2n-1?1) to +(2n-1?1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.

Abstract: A digital correction circuit calculates AD conversion errors EA and EA? in AD conversion stages subsequent to a target stage of AD conversion. EA is an error between an AD conversion result when a digital output of the target stage is set to 0, and an AD conversion result when it is set to +1 in a state where a higher reference voltage is input to the target stage. EB is an error between an AD conversion result when the digital output is set to 0, and an AD conversion result when it is set to ?1 in a state where a lower reference voltage is input to the target stage. The digital correction circuit adds a correcting value of the target stage to the digital output. The correcting value is ?(EA+EB)/2 when the digital output is ?1, ?(EA?EB)/2 when it is 0, and +(EA+EB)/2 when it is +1.