Patents by Inventor Takuma FUYUKI
Takuma FUYUKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230178965Abstract: A semiconductor stack includes a first-conductivity-type layer, a quantum well structure, and a second-conductivity-type layer. The first-conductivity-type layer, the quantum well structure, and the second-conductivity-type layer are stacked in this order. The quantum well structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. In the first semiconductor layer and the third semiconductor layer, compositions of the first semiconductor layer and the third semiconductor layer are changed such that a bandgap decreases toward the second semiconductor layer. Transition of an electron is possible between a conduction band of each of the first semiconductor layer and the third semiconductor layer and a valence band of the second semiconductor layer.Type: ApplicationFiled: October 27, 2022Publication date: June 8, 2023Inventors: Takuma FUYUKI, Susumu YOSHIMOTO
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Patent number: 11152521Abstract: A semiconductor laminate includes a substrate composed of InP, a first buffer layer composed of InP containing less than 1×1021 cm?3 Sb and disposed on the substrate, and a second buffer layer composed of InGaAs and disposed on the first buffer layer. The first buffer layer includes a first layer that has a higher concentration of Sb than the substrate and that is arranged to include a first main surface which is a main surface of the first buffer layer on the substrate side. The second buffer layer includes a second layer that has a lower concentration of Sb than the first layer and that is arranged to include a second main surface which is a main surface of the second buffer layer on the first buffer layer side.Type: GrantFiled: November 7, 2019Date of Patent: October 19, 2021Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma Fuyuki, Takashi Go, Takashi Ishizuka
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Semiconductor laminate, light-receiving element, and method for manufacturing semiconductor laminate
Patent number: 11081605Abstract: A semiconductor laminate includes a substrate formed of a group III-V compound semiconductor and a quantum well structure disposed on the substrate. The quantum well structure includes a second element layer formed of a group III-V compound semiconductor and containing Sb and a first element layer formed of a group III-V compound semiconductor and disposed in contact with the second element layer. In the first element layer, the thickness of a region in which the content of Sb decreases in a direction away from the substrate from 80% of the maximum content of Sb in the second element layer to 6% of the maximum content is from 0.5 nm to 3.0 nm inclusive.Type: GrantFiled: August 24, 2018Date of Patent: August 3, 2021Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma Fuyuki, Tomohiro Doi, Takashi Go, Takashi Ishizuka -
Patent number: 10790401Abstract: A semiconductor stacked body includes a base layer containing a III-V group compound semiconductor, a light-receiving layer containing a III-V group compound semiconductor, a control layer containing a III-V group compound semiconductor and disposed in contact with the light-receiving layer, a diffusion blocking layer containing a III-V group compound semiconductor and a p-type impurity that generates a p-type carrier, the diffusion blocking layer having a p-type impurity concentration of 1×1016 cm?3 or less, and a contact layer containing a III-V group compound semiconductor and having p-type conductivity. These layers are stacked in this order. The concentration of an element in the control layer, the element being identical to a group V element contained in the light-receiving layer, is lower on a main surface of the control layer adjacent to the diffusion blocking layer than on a main surface of the control layer adjacent to the light-receiving layer.Type: GrantFiled: May 9, 2019Date of Patent: September 29, 2020Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma Fuyuki, Takashi Go, Takashi Ishizuka
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Publication number: 20200227576Abstract: A semiconductor laminate includes a substrate composed of InP, a first buffer layer composed of InP containing less than 1×1021 cm?3 Sb and disposed on the substrate, and a second buffer layer composed of InGaAs and disposed on the first buffer layer. The first buffer layer includes a first layer that has a higher concentration of Sb than the substrate and that is arranged to include a first main surface which is a main surface of the first buffer layer on the substrate side. The second buffer layer includes a second layer that has a lower concentration of Sb than the first layer and that is arranged to include a second main surface which is a main surface of the second buffer layer on the first buffer layer side.Type: ApplicationFiled: November 7, 2019Publication date: July 16, 2020Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma FUYUKI, Takashi GO, Takashi ISHIZUKA
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Patent number: 10714640Abstract: A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 1×1014 cm?3 or more and 1×1017 cm?3 or less in the second semiconductor layer.Type: GrantFiled: January 24, 2017Date of Patent: July 14, 2020Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma Fuyuki, Suguru Arikata, Susumu Yoshimoto, Katsushi Akita
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SEMICONDUCTOR LAMINATE, LIGHT-RECEIVING ELEMENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LAMINATE
Publication number: 20200203542Abstract: A semiconductor laminate includes a substrate formed of a group III-V compound semiconductor and a quantum well structure disposed on the substrate. The quantum well structure includes a second element layer formed of a group III-V compound semiconductor and containing Sb and a first element layer formed of a group III-V compound semiconductor and disposed in contact with the second element layer. In the first element layer, the thickness of a region in which the content of Sb decreases in a direction away from the substrate from 80% of the maximum content of Sb in the second element layer to 6% of the maximum content is from 0.5 nm to 3.0 nm inclusive.Type: ApplicationFiled: August 24, 2018Publication date: June 25, 2020Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma FUYUKI, Tomohiro DOI, Takashi GO, Takashi ISHIZUKA -
Publication number: 20190355857Abstract: A semiconductor stacked body includes a base layer containing a III-V group compound semiconductor, a light-receiving layer containing a III-V group compound semiconductor, a control layer containing a III-V group compound semiconductor and disposed in contact with the light-receiving layer, a diffusion blocking layer containing a III-V group compound semiconductor and a p-type impurity that generates a p-type carrier, the diffusion blocking layer having a p-type impurity concentration of 1×1016 cm?3 or less, and a contact layer containing a III-V group compound semiconductor and having p-type conductivity. These layers are stacked in this order. The concentration of an element in the control layer, the element being identical to a group V element contained in the light-receiving layer, is lower on a main surface of the control layer adjacent to the diffusion blocking layer than on a main surface of the control layer adjacent to the light-receiving layer.Type: ApplicationFiled: May 9, 2019Publication date: November 21, 2019Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma FUYUKI, Takashi GO, Takashi ISHIZUKA
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Patent number: 10326034Abstract: A semiconductor layer includes a first semiconductor layer containing a III-V group compound semiconductor and having a first conductivity type, a quantum-well structure containing a III-V group compound semiconductor, a second semiconductor layer containing a III-V group compound semiconductor, a third semiconductor layer containing a III-V group compound semiconductor, and a fourth semiconductor layer containing a III-V group compound semiconductor and having a second conductivity type different from the first conductivity type. The first semiconductor layer, the quantum-well structure, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are stacked in this order. The concentration of an impurity that generates carriers of the second conductivity type is lower in the third semiconductor layer than in the fourth semiconductor layer.Type: GrantFiled: January 24, 2017Date of Patent: June 18, 2019Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Suguru Arikata, Takuma Fuyuki, Susumu Yoshimoto, Takashi Kyono, Katsushi Akita
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Publication number: 20190044010Abstract: A semiconductor layer includes a first semiconductor layer containing a III-V group compound semiconductor and having a first conductivity type, a quantum-well structure containing a III-V group compound semiconductor, a second semiconductor layer containing a III-V group compound semiconductor, a third semiconductor layer containing a III-V group compound semiconductor, and a fourth semiconductor layer containing a III-V group compound semiconductor and having a second conductivity type different from the first conductivity type. The first semiconductor layer, the quantum-well structure, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are stacked in this order. The concentration of an impurity that generates carriers of the second conductivity type is lower in the third semiconductor layer than in the fourth semiconductor layer.Type: ApplicationFiled: January 24, 2017Publication date: February 7, 2019Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Suguru ARIKATA, Takuma FUYUKI, Susumu YOSHIMOTO, Takashi KYONO, Katsushi AKITA
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Publication number: 20190035954Abstract: A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 1×1014 cm?3 or more and 1×1017 cm?3 or less in the second semiconductor layer.Type: ApplicationFiled: January 24, 2017Publication date: January 31, 2019Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma FUYUKI, Suguru ARIKATA, Susumu YOSHIMOTO, Katsushi AKITA
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Patent number: 10158035Abstract: A semiconductor stack includes a first-conductivity-type layer of a first conductivity type, the first-conductivity-type layer being formed of a III-V compound semiconductor; a quantum well light-receiving layer formed of a III-V compound semiconductor; and a second-conductivity-type layer of a second conductivity type different from the first conductivity type, the second-conductivity-type layer being formed of a III-V compound semiconductor. The first-conductivity-type layer, the quantum well light-receiving layer, and the second-conductivity-type layer are stacked in this order. The quantum well light-receiving layer has a thickness of 0.5 ?m or more. The quantum well light-receiving layer has a carrier concentration of 1×1016 cm?3 or less.Type: GrantFiled: April 8, 2016Date of Patent: December 18, 2018Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma Fuyuki, Suguru Arikata, Takashi Kyono, Yusuke Yoshizumi, Katsushi Akita
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Publication number: 20180122971Abstract: A semiconductor stack includes a first-conductivity-type layer of a first conductivity type, the first-conductivity-type layer being formed of a III-V compound semiconductor; a quantum well light-receiving layer formed of a III-V compound semiconductor; and a second-conductivity-type layer of a second conductivity type different from the first conductivity type, the second-conductivity-type layer being formed of a III-V compound semiconductor. The first-conductivity-type layer, the quantum well light-receiving layer, and the second-conductivity-type layer are stacked in this order. The quantum well light-receiving layer has a thickness of 0.5 ?m or more. The quantum well light-receiving layer has a carrier concentration of 1×1016 cm?3 or less.Type: ApplicationFiled: April 8, 2016Publication date: May 3, 2018Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma FUYUKI, Suguru ARIKATA, Takashi KYONO, Yusuke YOSHIZUMI, Katsushi AKITA