Patents by Inventor Takuma Ishida

Takuma Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11958497
    Abstract: A guidance device according to the present invention is installed in a movable body, the guidance device includes: an output device including a display device; an input device that receives an operation performed by an occupant of the movable body for starting each of a plurality of driving assistance functions installed in the movable body; and a guidance control device that determines whether the movable body is in a stopping period or in a traveling period, and allows the display device to display a video for explaining any one of the plurality of driving assistance functions when the movable body is in the stopping period.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: April 16, 2024
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Junya Obara, Sunao Yamaguchi, Takuma Minemura, Yusuke Ishida, Kenta Maruyama
  • Publication number: 20230415876
    Abstract: An outboard motor includes an engine, a propeller shaft, a propeller attached to the propeller shaft, a transmission to transmit rotation of the engine to the propeller shaft, an upper accommodation body accommodating a portion of the engine, a lower accommodation body accommodating a portion of the propeller shaft, and a steering to cause the lower accommodation body to rotate about a steering axis with respect to the upper accommodation body. The upper accommodation body includes an upper exhaust channel including an upper exhaust port that communicates with the engine. The lower accommodation body includes a lower exhaust channel including a lower exhaust port. The upper exhaust channel and the lower exhaust channel are switchable between a communication state of communicating with each other and a non-communication state of not communicating with each other based on a rudder angle of the steering.
    Type: Application
    Filed: December 13, 2022
    Publication date: December 28, 2023
    Inventors: Kimitaka SARUWATARI, Yu WAKAMIZU, Daisuke KOYAMA, Masashi HIROTA, Takuma ISHIDA
  • Publication number: 20230135883
    Abstract: A garbage collection watercraft includes a hull, a collection box, and a buoyant material. The collection box includes an intake port to receive garbage. The collection box is held by the hull so as to be movable between a collection position and a pull-up position. The collection box is at least partially located underwater at the collection position. The pull-up position is located higher than the collection position. The buoyant material is attached to the collection box. The buoyant material raises the collection box from the collection position to the pull-up position by a buoyant force.
    Type: Application
    Filed: August 11, 2022
    Publication date: May 4, 2023
    Inventors: Takuma ISHIDA, Junya TSUKADA, Junya ONOUE
  • Patent number: 8196350
    Abstract: A window regulator assembly is described that comprises a window bracket that is in contact with the bottom edge of the window; a cable; a carrier plate that is in contact with the window bracket and both ends of the cable; a tension spring located on each end of the cable; an upper bracket assembly; a drum housing having a cable drum; a hollow conduit located between the upper bracket assembly and the drum housing; and a drive unit. The upper bracket assembly, cable drum, and conduit are capable of slideably receiving the cable, while the tension springs provide a predetermined amount of tension to the cable in order for the window regulator assembly to move the window between open and closed positions. Many of the components of the window regulator assembly may be formed from a thermoplastic material.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: June 12, 2012
    Assignee: Hi-Lex Controls, Inc.
    Inventors: Shigeki Arimoto, Takuma Ishida
  • Patent number: 7982541
    Abstract: A count control signal generating section for generating a count control signal on the basis of an output signal of a variable gain amplifier; an up/down counter for performing an up-count operation or a down-count operation on the basis of the count control signal; a gain control signal generating section for generating a gain control signal to be supplied to the variable gain amplifier on the basis of a count value of the up/down counter; and a state detector section for outputting a state detection signal indicating whether a state of a circuit operation is a steady state or another state are provided. When the state detection signal indicates that the state of the circuit operation is the steady state, the operation of at least one of the up/down counter and the gain control signal generating section is controlled so as to fix the gain control signal.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Takayuki Nakai, Takuma Ishida
  • Publication number: 20100259330
    Abstract: A count control signal generating section for generating a count control signal on the basis of an output signal of a variable gain amplifier; an up/down counter for performing an up-count operation or a down-count operation on the basis of the count control signal; a gain control signal generating section for generating a gain control signal to be supplied to the variable gain amplifier on the basis of a count value of the up/down counter; and a state detector section for outputting a state detection signal indicating whether a state of a circuit operation is a steady state or another state are provided. When the state detection signal indicates that the state of the circuit operation is the steady state, the operation of at least one of the up/down counter and the gain control signal generating section is controlled so as to fix the gain control signal.
    Type: Application
    Filed: April 9, 2010
    Publication date: October 14, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Takayuki Nakai, Takuma Ishida
  • Patent number: 7795967
    Abstract: There is provided an AGC circuit that has a very small offset voltage and is easy for integration, without using any of external capacities.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Takayuki Nakai, Takuma Ishida
  • Publication number: 20100223852
    Abstract: A window regulator assembly is described that comprises a window bracket that is in contact with the bottom edge of the window; a cable; a carrier plate that is in contact with the window bracket and both ends of the cable; a tension spring located on each end of the cable; an upper bracket assembly; a drum housing having a cable drum; a hollow conduit located between the upper bracket assembly and the drum housing; and a drive unit. The upper bracket assembly, cable drum, and conduit are capable of slideably receiving the cable, while the tension springs provide a predetermined amount of tension to the cable in order for the window regulator assembly to move the window between open and closed positions. Many of the components of the window regulator assembly may be formed from a thermoplastic material.
    Type: Application
    Filed: March 6, 2009
    Publication date: September 9, 2010
    Inventors: Shigeki Arimoto, Takuma Ishida
  • Patent number: 7595692
    Abstract: An automatic gain control circuit for controlling the gain of a variable gain amplifier block includes a count control signal generating block, an up-down counter, a gain control signal generating block, and a downcount clock signal generating block. The up-down counter upcounts an upcount clock signal or downcounts a downcount clock signal according to a count control signal generated by the count control signal generating block. The gain control signal generating block generates a gain control signal corresponding to a count value of the up-down counter. The downcount clock signal generating block generates a downcount clock signal whose frequency corresponds to the count value of the up-down counter.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: September 29, 2009
    Assignee: Panasonic Corporation
    Inventor: Takuma Ishida
  • Publication number: 20090096528
    Abstract: There is provided an AGC circuit that has a very small offset voltage and is easy for integration, without using any of external capacities.
    Type: Application
    Filed: March 19, 2008
    Publication date: April 16, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Takayuki Nakai, Takuma Ishida
  • Patent number: 7443242
    Abstract: An AGC circuit includes: a variable gain amplifier circuit having a gain controlled with a gain control signal; a rectifier circuit for rectifying an output signal of the variable gain amplifier circuit; a voltage comparator for comparing a rectified signal with a threshold voltage; an up/down counter that switches between up-counting and down-counting according to the level of an output voltage of the voltage comparator; and a D/A converter circuit for outputting a voltage corresponding to a count value of the up/down counter. The gain control signal supplied to the variable gain amplifier circuit corresponds to the voltage output from the D/A converter circuit, and the threshold voltage for the voltage comparator is a voltage corresponding to the voltage output from the D/A converter circuit.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 28, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Takuma Ishida
  • Publication number: 20080218268
    Abstract: An automatic gain control circuit for controlling the gain of a variable gain amplifier block includes a count control signal generating block, an up-down counter, a gain control signal generating block, and a downcount clock signal generating block. The up-down counter upcounts an upcount clock signal or downcounts a downcount clock signal according to a count control signal generated by the count control signal generating block. The gain control signal generating block generates a gain control signal corresponding to a count value of the up-down counter. The downcount clock signal generating block generates a downcount clock signal whose frequency corresponds to the count value of the up-down counter.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 11, 2008
    Inventor: Takuma Ishida
  • Patent number: 7411456
    Abstract: An AGC circuit includes: a variable gain amplifier circuit having a gain controlled with a gain control signal; a rectifier circuit for rectifying an output signal of the variable gain amplifier circuit; a voltage comparator for comparing a rectified signal with a threshold voltage; an up/down counter that switches between up-counting and down-counting according to the level of an output voltage of the voltage comparator; and a D/A converter circuit for outputting a voltage corresponding to a count value of the up/down counter. The gain control signal supplied to the variable gain amplifier circuit corresponds to the voltage output from the D/A converter circuit, and the threshold voltage for the voltage comparator is a voltage corresponding to the voltage output from the D/A converter circuit.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: August 12, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Takuma Ishida
  • Publication number: 20080074185
    Abstract: An AGC circuit includes: a variable gain amplifier circuit having a gain controlled with a gain control signal; a rectifier circuit for rectifying an output signal of the variable gain amplifier circuit; a voltage comparator for comparing a rectified signal with a threshold voltage; an up/down counter that switches between up-counting and down-counting according to the level of an output voltage of the voltage comparator; and a D/A converter circuit for outputting a voltage corresponding to a count value of the up/down counter. The gain control signal supplied to the variable gain amplifier circuit corresponds to the voltage output from the D/A converter circuit, and the threshold voltage for the voltage comparator is a voltage corresponding to the voltage output from the D/A converter circuit.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 27, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
    Inventor: Takuma Ishida
  • Publication number: 20070064953
    Abstract: This speaker protection circuit includes: a voltage comparator that compares a voltage of a reference bias terminal of an amplifying circuit constituting a BTL amplifying device with a preset threshold voltage; and first and second switches for switching between a mode of supplying an electric current to each of two power amplifying circuits and a mode of cutting off the electric current. When the voltage of the reference bias terminal is lower than the threshold voltage, based on an output level of the voltage comparator, at least one of the first and second switches is turned off to cut off a current supply to each of the power amplifying circuits so that driving of a speaker by the power amplifying circuits is halted. Thus, it is possible to suppress, using a relatively simple configuration, an offset current generated in a speaker due to an abnormality of the voltage of a reference bias terminal.
    Type: Application
    Filed: September 20, 2006
    Publication date: March 22, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takuma ISHIDA, Makoto YAMAMOTO
  • Patent number: 7015759
    Abstract: An AGC circuit of the present invention includes a first up/down counter for converting the amount of change in an output voltage higher than a threshold voltage into a count value and controlling a gain of a variable gain amplifier circuit and a second up/down counter to which a reference clock having a lower frequency than that of a reference clock supplied to the first up/down counter is supplied. Count values of the first and second up/down counters are D/A-converted and then compared with each other by a voltage comparator. An up/down count of the first up/down counter is controlled based on a comparison result and the gain of the variable gain amplifier circuit is controlled using only a signal based on the count value of the first up/down counter, thereby suppressing distortion of an output waveform and the generation of a frequency signal which is not originally input.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: March 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takuma Ishida, Keiichi Fujii
  • Publication number: 20060044065
    Abstract: An AGC circuit includes: a variable gain amplifier circuit having a gain controlled with a gain control signal; a rectifier circuit for rectifying an output signal of the variable gain amplifier circuit; a voltage comparator for comparing a rectified signal with a threshold voltage; an up/down counter that switches between up-counting and down-counting according to the level of an output voltage of the voltage comparator; and a D/A converter circuit for outputting a voltage corresponding to a count value of the up/down counter. The gain control signal supplied to the variable gain amplifier circuit corresponds to the voltage output from the D/A converter circuit, and the threshold voltage for the voltage comparator is a voltage corresponding to the voltage output from the D/A converter circuit.
    Type: Application
    Filed: August 10, 2005
    Publication date: March 2, 2006
    Inventor: Takuma Ishida
  • Patent number: 6977550
    Abstract: An AGC circuit, which does not require any signal integration circuit comprised of a capacitor and a resistor, is provided. To achieve the above object, when amplifying or attenuating input signal by a variable gain control circuit controlled by the gain control voltage, output signal of the variable gain amplifier circuit is rectified by a rectification circuit, the output signal of the rectification circuit is compared to an arbitrary set voltage by a voltage comparator. The up-count operation and the down-count operation of the up/down counter is controlled to changeover by the output signal of the voltage comparator, and a voltage corresponding to the count value of the up/down counter is output from the D/A conversion circuit. Thus, gain control voltage corresponding to the voltage output from the D/A conversion circuit is supplied to the variable gain amplifier circuit.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: December 20, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takuma Ishida, Taku Kobayashi, Keiichi Fujii
  • Patent number: 6972619
    Abstract: In order that an amplifier with a gain proportional to source voltage is obtained, the drain-source voltages of first and second P-channel MOS-FETs are zero-biased, and a voltage shifted higher by the amount of the threshold voltage of the P-channel MOS-FET on the basis of a voltage obtained by dividing the power source voltage by resistors is applied to the positive input terminal of an operational amplifier. The gate of one of the first and second MOS-FETs is connected to a circuit ground, and a negative fixed voltage with reference to the potential obtained by dividing the power source voltage by resistors is applied to the gate of the other MOS-FET. The ON resistances of the two MOS-FETs are used as the input resistor and the feedback resistor of the operational amplifier, respectively.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: December 6, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaharu Sato, Takuma Ishida, Taku Kobayashi
  • Patent number: 6891407
    Abstract: A rectified analog input signal is compared with a threshold voltage by a voltage comparator, and counting direction of an up/down counter is switched based on the comparison result, and a latch circuit retains an output of the up/down counter, and then an analog-digital converting circuit converts an output of the latch signal into a direct-current voltage. In addition, two input terminals, to which a clock for up-count operation and a clock for down-count operation are independently provided, is provided in the up/down counter, and a timing pulse generating circuit for determining reset timing of the up/down counting circuit and latch timing of the latch circuit is provided.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: May 10, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Taku Kobayashi, Keiichi Fujii, Takuma Ishida