Patents by Inventor Takumi FUNAYAMA

Takumi FUNAYAMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Output circuit, transmission circuit, and semiconductor integrated circuit
    Patent number: 11791820
    Abstract: An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: October 17, 2023
    Assignee: SOCIONEXT INC.
    Inventors: Takumi Funayama, Akiyoshi Matsuda
  • OUTPUT CIRCUIT, TRANSMISSION CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20220407519
    Abstract: An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.
    Type: Application
    Filed: August 25, 2022
    Publication date: December 22, 2022
    Inventors: Takumi FUNAYAMA, Akiyoshi MATSUDA