Abstract: A memory control apparatus that includes a queue to store up to 2 access requests to a memory and a command issuer to issue a command to the memory according to access requests stored to the queue. The command issuer includes an address comparator to evaluate whether the access requests stored to the queue are for a same page of the memory. If the access requests are for a same page, the command issuer consecutively issues read/write commands, whereas if the access requests are for different pages, the command issuer issues a pre-charge command after issuing one read command.

Abstract: A data processing apparatus adopting a pipeline processing system, includes an instruction memory which store instruction packets; and a processing unit configured to execute the instruction packets sequentially in a pipeline manner. The processing unit includes an instruction queue and a loop speed-up circuit. The instruction packets stored in the instruction queue are executed sequentially by the processing unit. The loop speed-up circuit stores the instruction packets read out from the instruction memory into the instruction queue sequentially, holds the instruction packet containing a loop start address for a loop process, and outputs the held instruction packet to the instruction queue, when a loop process end is detected and the loop process is not circulated for a predetermined number of times.