Patents by Inventor Takumi Ueno
Takumi Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7150947Abstract: A photosensitive polymer composition, having (a) a polymer selected from polyimide precursors and polyimides having an acid group protected by a protecting group and having no amino group (—NH2) at the end; and (b) a compound that generates an acid when exposed to light and capable of deprotecting the protecting group from the acid group, is employed to form layers of a semiconductor device.Type: GrantFiled: May 19, 2003Date of Patent: December 19, 2006Assignees: Hitachi Chemical Dupont Microsystems Ltd., Hitachi Chemical Dupont Microsystems LLC.Inventors: Masataka Nunomura, Masayuki Ooe, Hajime Nakano, Yoshiko Tsumaru, Takumi Ueno
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Patent number: 7038325Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.Type: GrantFiled: April 23, 2004Date of Patent: May 2, 2006Assignees: Hitachi Cable, Ltd., Renesas Technology Corp.Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
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Patent number: 6940162Abstract: In a multi chip module of a structure wherein a plurality of bare or packaged semiconductor chips are mounted on a single wiring board and upper surfaces of the semiconductor chips are covered with a single heat spread plate, the whole space around the semiconductor chips thus sandwiched between the wiring board and the heat spread plate is filled with resin. By so doing, the semiconductor chips are interconnected through the resin, so that even if a stress is exerted on any of the chips, it is dispersed and therefore it is possible to diminish the occurrence of cracks in the chips and the heat spread plate caused by stress concentration. Besides, since the semiconductor chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.Type: GrantFiled: May 7, 2004Date of Patent: September 6, 2005Assignee: Renesas Technology Corp.Inventors: Shuji Eguchi, Akira Nagai, Haruo Akahoshi, Takumi Ueno, Toshiya Satoh, Masahiko Ogino, Asao Nishimura, Ichiro Anjo, Hideki Tanaka
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Patent number: 6924971Abstract: A high dielectric composite material obtained by subjecting submicron particles of an inorganic filler containing a metal as its essential component to an insulating treatment such as a chemical treatment, further subjecting to a surface treatment for improving their compatibility with organic resins, and then dispersing in an organic resin, has a dielectric constant of 15 or above, with its dielectric loss tangent in the frequency region of from 100 MHz to 80 GHz being 0.1 or less, and can therefore be used effectively for multilayer wiring boards and module substrates.Type: GrantFiled: August 7, 2002Date of Patent: August 2, 2005Assignee: Hitachi, Ltd.Inventors: Yuichi Satsu, Akio Takahashi, Tadashi Fujieda, Takumi Ueno, Haruo Akahoshi
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Patent number: 6888230Abstract: Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on the same plane.Type: GrantFiled: October 28, 1999Date of Patent: May 3, 2005Assignee: Renesas Technology Corp.Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
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Publication number: 20040251540Abstract: In a multi chip module of a structure wherein a plurality of bare or packaged semiconductor chips are mounted on a single wiring board and upper surfaces of the semiconductor chips are covered with a single heat spread plate, the whole space around the semiconductor chips thus sandwiched between the wiring board and the heat spread plate is filled with resin.Type: ApplicationFiled: May 7, 2004Publication date: December 16, 2004Inventors: Shuji Eguchi, Akira Nagai, Haruo Akahoshi, Takumi Ueno, Toshiya Satoh, Masahiko Ogino, Asao Nishimura, Ichiro Anjo, Hideki Tanaka
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Publication number: 20040217453Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility.Type: ApplicationFiled: June 7, 2004Publication date: November 4, 2004Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
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Publication number: 20040195702Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.Type: ApplicationFiled: April 23, 2004Publication date: October 7, 2004Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
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Patent number: 6784541Abstract: In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the chips are covered with a single heat spread plate, and the whole space around the chips sandwiched between the wiring board and the heat spread plate is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.Type: GrantFiled: November 25, 2002Date of Patent: August 31, 2004Assignee: Hitachi, Ltd.Inventors: Shuji Eguchi, Akira Nagai, Haruo Akahoshi, Takumi Ueno, Toshiya Satoh, Masahiko Ogino, Asao Nishimura, Ichiro Anjo, Hideki Tanaka
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Patent number: 6710263Abstract: In a semiconductor device, the likely occurrence of cracking of a ceramic substrate, and the consequential disconnection of internal layer wiring, due to thermal changes suffered when the semiconductor device is mounted on external wiring boards having different thermal expansion is prevented. The semiconductor device has a ceramic substrate, a wiring pattern formed on a first principal plane and having mounted semiconductor components, an external electrode portion formed on a second principal plane and connected to an external circuit, internal layer wiring formed inside said ceramic substrate to electrically connect said wiring pattern and said external electrode portion via through-hole wiring, and semiconductor components and a resin layer covering said semiconductor components, wherein the internal layer wiring is formed internally with respect to the side of said ceramic substrate with a clearance of at least 0.05 mm.Type: GrantFiled: February 23, 2001Date of Patent: March 23, 2004Assignees: Renesas Technology Corporation, Hitachi Tohbu Semiconductors, Ltd.Inventors: Toshiyuki Kobayashi, Yasutoshi Kurihara, Takumi Ueno, Nobuyoshi Maejima, Hirokazu Nakajima, Tomio Yamada, Tsuneo Endoh
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Patent number: 6710446Abstract: A semiconductor device and a manufacturing method thereof, which device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the semiconductor element, bump electrodes for electrically connecting to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relaxation layer being adhered thereto, wherein more than one third of the stress relaxation layer from a surface thereof is cut away for removal and wherein the stress relaxation layer is subdivided into a plurality of regions. Accordingly, it is possible to provide a semiconductor device capable of offering high density mounting schemes with increased reliability while reducing production costs.Type: GrantFiled: May 2, 2002Date of Patent: March 23, 2004Assignee: Renesas Technology CorporationInventors: Akira Nagai, Takumi Ueno, Haruo Akahoshi, Syuji Eguchi, Masahiko Ogino, Toshiya Satoh, Asao Nishimura, Ichiro Anjoh
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Publication number: 20040029045Abstract: A photosensitive polymer composition, having (a) a polymer selected from polyimide precursors and polyimides having an acid group protected by a protecting group and having no amino group (—NH2) at the end; and (b) a compound that generates an acid when exposed to light and capable of deprotecting the protecting group from the acid group, is employed to form layers of a semiconductor device.Type: ApplicationFiled: May 19, 2003Publication date: February 12, 2004Inventors: Masataka Nunomura, Masayuki Ooe, Hajime Nakano, Yoshiko Tsumaru, Takumi Ueno
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Publication number: 20030201530Abstract: To provide a composite material member for semiconductor device, an insulated semiconductor device and non-insulated semiconductor device using the composite material member, which are effective for obtaining a semiconductor device that alleviates thermal stress or thermal strain occurring during production or operation, has no possibilities of deformation, degeneration and rupture of each member, and is highly reliably and inexpensive. The composite material member for semiconductor device is characterized by being a composite metal plate with particles composed of cuprous oxide dispersed in a copper matrix, in which a surface of the composite metal plate is covered with a metal layer, and a copper layer with thickness of 0.5 &mgr;m or larger exists in an interface formed by the composite metal plate and the metal layer.Type: ApplicationFiled: May 5, 2003Publication date: October 30, 2003Applicant: Hitachi, Ltd.Inventors: Yasutoshi Kurihara, Yasuo Kondo, Takumi Ueno, Toshiaki Morita, Kenji Koyama, Takashi Suzumura, Kazuhiko Nakagawa, Kunihiro Fukuda
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Patent number: 6638631Abstract: The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of −50° C. to 300° C., has an elastic modulus at room temperature of 2-0.01 GPa and is high in reliability of electric insulation regardless of a temperature fluctuation, and provides a semiconductor device using the same. The present invention also provides a thermal stable low elastic modulus resin composition obtained by heat-curing a mixture containing a polyimide, polyamide-imide or polyamide resin or resin precursor, whose cured product has an elastic modulus measured at −50° C. of 2-0.01 GPa, and an oligomer of an organosilicon compound having a functional group capable of causing addition reaction with an NH and/or COOH group.Type: GrantFiled: July 5, 2002Date of Patent: October 28, 2003Assignee: Hitachi, ltd.Inventors: Yuichi Satsu, Morimichi Umino, Takumi Ueno, Akio Takahashi, Akira Nagai, Toshiya Satoh, Shinji Yamada, Kazuhiro Suzuki
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Patent number: 6638352Abstract: The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of −50° C. to 300° C., has an elastic modulus at room temperature of 2-0.01 GPa and is high in reliability of electric insulation regardless of a temperature fluctuation, and provides a semiconductor device using the same. The present invention also provides a thermal stable low elastic modulus resin composition obtained by heat-curing a mixture containing a polyimide, polyamide-imide or polyamide resin or resin precursor, whose cured product has an elastic modulus measured at −50° C. of 2-0.01 GPa, and an oligomer of an organosilicon compound having a functional group capable of causing addition reaction with an NH and/or COOH group.Type: GrantFiled: March 15, 2002Date of Patent: October 28, 2003Assignee: Hitachi, Ltd.Inventors: Yuichi Satsu, Morimichi Umino, Takumi Ueno, Akio Takahashi, Akira Nagai, Toshiya Satoh, Shinji Yamada, Kazuhiro Suzuki
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Patent number: 6627997Abstract: In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the semiconductor chips are covered with a single heat spread plate, and the whole space around the semiconductor chips, sandwiched between the wiring board and the heat spread plate, is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the semiconductor chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.Type: GrantFiled: January 27, 2000Date of Patent: September 30, 2003Assignee: Hitachi, Ltd.Inventors: Shuji Eguchi, Akira Nagai, Haruo Akahoshi, Takumi Ueno, Toshiya Satoh, Masahiko Ogino, Asao Nishimura, Ichiro Anjo, Hideki Tanaka
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Patent number: 6579623Abstract: To provide a composite material member for semiconductor device, an insulated semiconductor device and non-insulated semiconductor device using the composite material member, which are effective for obtaining a semiconductor device that alleviates thermal stress or thermal strain occurring during production or operation, has no possibilities of deformation, degeneration and rupture of each member, and is highly reliably and inexpensive. The composite material member for semiconductor device is characterized by being a composite metal plate with particles composed of cuprous oxide dispersed in a copper matrix, in which a surface of the composite metal plate is covered with a metal layer, and a copper layer with thickness of 0.5 &mgr;m or larger exists in an interface formed by the composite metal plate and the metal layer.Type: GrantFiled: February 27, 2002Date of Patent: June 17, 2003Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.Inventors: Yasutoshi Kurihara, Yasuo Kondo, Takumi Ueno, Toshiaki Morita, Kenji Koyama, Takashi Suzumura, Kazuhiko Nakagawa, Kunihiro Fukuda
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Publication number: 20030071348Abstract: In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the chips are covered with a single heat spread plate, and the whole space around the chips sandwiched between the wiring board and the heat spread plate is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.Type: ApplicationFiled: November 25, 2002Publication date: April 17, 2003Inventors: Shuji Eguchi, Akira Nagai, Haruo Akahoshi, Takumi Ueno, Toshiya Satoh, Masahiko Ogino, Asao Nishimura, Ichiro Anjo, Hideki Tanaka
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Publication number: 20030049193Abstract: The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of −50° C. to 300° C., has an elastic modulus at room temperature of 2-0.01 GPa and is high in reliability of electric insulation regardless of a temperature fluctuation, and provides a semiconductor device using the same.Type: ApplicationFiled: March 15, 2002Publication date: March 13, 2003Inventors: Yuichi Satsu, Morimichi Umino, Takumi Ueno, Akio Takahashi, Akira Nagai, Toshiya Satoh, Shinji Yamada, Kazuhiro Suzuki
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Publication number: 20030047351Abstract: The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of −50° C. to 300° C., has an elastic modulus at room temperature of 2-0.01 GPa and is high in reliability of electric insulation regardless of a temperature fluctuation, and provides a semiconductor device using the same.Type: ApplicationFiled: July 5, 2002Publication date: March 13, 2003Inventors: Yuichi Satsu, Morimichi Umino, Takumi Ueno, Akio Takahashi, Akira Nagai, Toshiya Satoh, Shinji Yamada, Kazuhiro Suzuki