Patents by Inventor Takuro Asazu
Takuro Asazu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7320932Abstract: A semiconductor device of the present invention is furnished with (a) a first protection film, formed on a substrate, having an opening section on an electrode pad, (b) a protrusion electrode, connected on the electrode pad at the opening section, whose peripheral portion is formed to overlap the first protection film, (c) a second protection film, formed to cover at least a gap at a boundary portion of the first protection film and the protrusion electrode, having an opening on a top area of the protrusion electrode except a portion around the boundary portion of the first protection film and the protrusion electrode, and (d) a coating layer formed to cover a surface of the protrusion electrode at the opening of the second protection film. With this arrangement, it is possible to provide a semiconductor device wherein the protrusion electrode is formed with an electroless plating method, capable of preventing the lowering of the adhesion strength of the protrusion electrode to the electrode pad.Type: GrantFiled: March 20, 2006Date of Patent: January 22, 2008Assignee: Sharp Kabushiki KaishaInventors: Shinji Yamaguchi, Takuro Asazu, Atsushi Ono
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Publication number: 20060157850Abstract: A semiconductor device of the present invention is furnished with (a) a first protection film, formed on a substrate, having an opening section on an electrode pad, (b) a protrusion electrode, connected on the electrode pad at the opening section, whose peripheral portion is formed to overlap the first protection film, (c) a second protection film, formed to cover at least a gap at a boundary portion of the first protection film and the protrusion electrode, having an opening on a top area of the protrusion electrode except a portion around the boundary portion of the first protection film and the protrusion electrode, and (d) a coating layer formed to cover a surface of the protrusion electrode at the opening of the second protection film. With this arrangement, it is possible to provide a semiconductor device wherein the protrusion electrode is formed with an electroless plating method, capable of preventing the lowering of the adhesion strength of the protrusion electrode to the electrode pad.Type: ApplicationFiled: March 20, 2006Publication date: July 20, 2006Applicant: Sharp Kabushiki KaishaInventors: Shinji Yamaguchi, Takuro Asazu, Atsushi Ono
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Patent number: 7045894Abstract: A semiconductor device of the present invention is furnished with (a) a first protection film, formed on a substrate, having an opening section on an electrode pad, (b) a protrusion electrode, connected on the electrode pad at the opening section, whose peripheral portion is formed to overlap the first protection film, (c) a second protection film, formed to cover at least a gap at a boundary portion of the first protection film and the protrusion electrode, having an opening on a top area of the protrusion electrode except a portion around the boundary portion of the first protection film and the protrusion electrode, and (d) a coating layer formed to cover a surface of the protrusion electrode at the opening of the second protection film. With this arrangement, it is possible to provide a semiconductor device wherein the protrusion electrode is formed with an electroless plating method, capable of preventing the lowering of the adhesion strength of the protrusion electrode to the electrode pad.Type: GrantFiled: December 24, 2002Date of Patent: May 16, 2006Assignee: Sharp Kabushiki KaishaInventors: Shinji Yamaguchi, Takuro Asazu, Atsushi Ono
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Patent number: 6908311Abstract: A first protection film (3) and a second protection film (4) are formed on an electrode pad (2). Bumps (5) are formed at sites where the deposited first and second protection films (3), (4) are both removed. The openings (3a) where the lower, first protection film (3) is removed are larger than the openings (4a) where the upper, second protection film (4) is removed, so that the upper, second protection film (4) has an overhanging structure. The bottom periphery of the bump (5) is formed to extend under the second protection film (4).Type: GrantFiled: April 25, 2003Date of Patent: June 21, 2005Assignee: Sharp Kabushiki KaishaInventors: Atsushi Ono, Takuro Asazu, Shinji Yamaguchi
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Patent number: 6747351Abstract: A defect-free film is formed on a surface of a protrusive electrode. An immersion Au film is formed on the surface of the protrusive electrode, after a gap which an immersion Au plating liquid can enter evenly is formed between a protrusive electrode made of Ni or a Ni alloy on an electrode pad made of Al or mainly made of Al and a protective coat by etching.Type: GrantFiled: October 5, 2001Date of Patent: June 8, 2004Assignee: Sharp Kabushiki KaishaInventors: Shinji Yamaguchi, Takuro Asazu, Atsushi Ono
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Publication number: 20030203661Abstract: A first protection film (3) and a second protection film (4) are formed on an electrode pad (2). Bumps (5) are formed at sites where the deposited first and second protection films (3), (4) are both removed. The openings (3a) where the lower, first protection film (3) is removed are larger than the openings (4a) where the upper, second protection film (4) is removed, so that the upper, second protection film (4) has an overhanging structure. The bottom periphery of the bump (5) is formed to extend under the second protection film (4).Type: ApplicationFiled: April 25, 2003Publication date: October 30, 2003Inventors: Atsushi Ono, Takuro Asazu, Shinji Yamaguchi
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Publication number: 20030116865Abstract: A semiconductor device of the present invention is furnished with (a) a first protection film, formed on a substrate, having an opening section on an electrode pad, (b) a protrusion electrode, connected on the electrode pad at the opening section, whose peripheral portion is formed to overlap the first protection film, (c) a second protection film, formed to cover at least a gap at a boundary portion of the first protection film and the protrusion electrode, having an opening on a top area of the protrusion electrode except a portion around the boundary portion of the first protection film and the protrusion electrode, and (d) a coating layer formed to cover a surface of the protrusion electrode at the opening of the second protection film. With this arrangement, it is possible to provide a semiconductor device wherein the protrusion electrode is formed with an electroless plating method, capable of preventing the lowering of the adhesion strength of the protrusion electrode to the electrode pad.Type: ApplicationFiled: December 24, 2002Publication date: June 26, 2003Inventors: Shinji Yamaguchi, Takuro Asazu, Atsushi Ono
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Patent number: 6518162Abstract: The present invention includes a step of forming an Ni bump by non-electrolytic plating in an opening of a protecting film having an insulating property formed on an electrode pad which is provided on a semiconductor substrate, and a step of removing a plating solution residue remaining in a gap between the Ni bump and the protecting film. The plating solution residue is removed by cleaning in a cleaning solution containing hydrogen peroxide, or by applying an ultrasonic wave in a cleaning solution such as pure water.Type: GrantFiled: August 24, 2001Date of Patent: February 11, 2003Assignee: Sharp Kabushiki KaishaInventors: Atsushi Ono, Takuro Asazu, Shinji Yamaguchi
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Publication number: 20020081843Abstract: A defect-free film is formed on a surface of a protrusive electrode. An immersion Au film is formed on the surface of the protrusive electrode, after a gap which an immersion Au plating liquid can enter evenly is formed between a protrusive electrode made of Ni or a Ni alloy on an electrode pad made of Al or mainly made of Al and a protective coat by etching.Type: ApplicationFiled: October 5, 2001Publication date: June 27, 2002Inventors: Shinji Yamaguchi, Takuro Asazu, Atsushi Ono
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Publication number: 20020058412Abstract: The present invention includes a step of forming an Ni bump by non-electrolytic plating in an opening of a protecting film having an insulating property formed on an electrode pad which is provided on a semiconductor substrate, and a step of removing a plating solution residue remaining in a gap between the Ni bump and the protecting film. The plating solution residue is removed by cleaning in a cleaning solution containing hydrogen peroxide, or by applying an ultrasonic wave in a cleaning solution such as pure water.Type: ApplicationFiled: August 24, 2001Publication date: May 16, 2002Inventors: Atsushi Ono, Takuro Asazu, Shinji Yamaguchi
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Publication number: 20010017412Abstract: Formed on the semiconductor chip surface are electrode pads, on which electroless Ni plated bumps are formed. The electroless Ni plated bumps are arranged in at least two rows in parallel with the two sides of the semiconductor chip, opposing each other. Each electroless Ni bump is 5 &mgr;m or more in height and the surface is coated with Au plating as a metal film. The surface of the conductor leads is coated with Sn plating. The conductor leads and bumps are heated and pressed by a bonding tool to crate Au/Sn eutectic alloy junctions.Type: ApplicationFiled: December 5, 2000Publication date: August 30, 2001Inventors: Takuro Asazu, Atsushi Ono, Shinji Yamaguchi
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Patent number: 6049121Abstract: A tape carrier package includes a semiconductor chip including a first row of electrode bumps formed on a surface of a semiconductor chip and a second row of electrode bumps formed on the surface of the semiconductor chip parallel to the first row. The tape carrier package also includes an insulating film, at least a portion of the insulating film being formed on the semiconductor chip, a conductor pattern including a first lead section formed on the insulating film and connectable to an external device and a second lead section extending from the first lead section so as to electrically connect to the first and second rows of electrode bumps. At least a part of the first lead section is positioned on the semiconductor chip. A sealing resin is provided for sealing at least a junction between the first and second rows of electrode bumps and the second lead section.Type: GrantFiled: April 24, 1997Date of Patent: April 11, 2000Assignee: Sharp Kabushiki KaishaInventors: Kenji Toyosawa, Takuro Asazu, Naoyuki Tajima